233 lines
25 KiB
Text
233 lines
25 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1300701 # Simulator instruction rate (inst/s)
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host_mem_usage 208132 # Number of bytes of host memory used
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host_seconds 143.02 # Real time elapsed on the host
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host_tick_rate 1622346657 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 186027114 # Number of instructions simulated
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sim_seconds 0.232029 # Number of seconds simulated
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sim_ticks 232029492000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 29639490 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 36204000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000023 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 690 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 34134000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 690 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 12386694 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 12385567 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 63112000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000091 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1127 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 59731000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000091 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1127 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 23477.700559 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 42026874 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 54659.328564 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 42025057 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 99316000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1817 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 93865000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1817 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.333153 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 1364.595461 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 42026874 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 54659.328564 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 42025057 # number of overall hits
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system.cpu.dcache.overall_miss_latency 99316000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1817 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 93865000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1817 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 40 # number of replacements
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system.cpu.dcache.sampled_refs 1790 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 1364.595461 # Cycle average of tags in use
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system.cpu.dcache.total_refs 42025084 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 16 # number of writebacks
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.icache.ReadReq_accesses 189792839 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 189789788 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 3051 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 106179000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000016 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 3051 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 62205.764667 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 189792839 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 37801.376598 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
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system.cpu.icache.demand_hits 189789788 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 115332000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses
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system.cpu.icache.demand_misses 3051 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 106179000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000016 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 3051 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.560534 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 1147.972858 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 189792839 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 189789788 # number of overall hits
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system.cpu.icache.overall_miss_latency 115332000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses
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system.cpu.icache.overall_misses 3051 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 106179000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000016 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 3051 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 1506 # number of replacements
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system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1147.972858 # Cycle average of tags in use
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system.cpu.icache.total_refs 189789788 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 1100 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 57200000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 1100 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 44000000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 1100 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 3741 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 1380 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 122772000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.631115 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 2361 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631115 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 27 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 1404000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 27 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1080000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 27 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.588813 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 4841 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 1380 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 179972000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.714935 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 3461 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 138440000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.714935 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 3461 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::0 0.050372 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_%::1 0.000062 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::0 1650.604772 # Average occupied blocks per context
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system.cpu.l2cache.occ_blocks::1 2.043757 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 4841 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 1380 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 179972000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.714935 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 3461 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 138440000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.714935 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 3461 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 2342 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 1652.648529 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 464058984 # number of cpu cycles simulated
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system.cpu.num_insts 186027114 # Number of instructions executed
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system.cpu.num_refs 42511846 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
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---------- End Simulation Statistics ----------
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