625854785b
Some subset of UpgradeReq messages shifted to the new SCUpgradeReq type. Other than that there are no significant differences.
1416 lines
159 KiB
Text
1416 lines
159 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 198866 # Simulator instruction rate (inst/s)
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host_mem_usage 278256 # Number of bytes of host memory used
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host_seconds 282.46 # Real time elapsed on the host
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host_tick_rate 6753860070 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 56171530 # Number of instructions simulated
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sim_seconds 1.907689 # Number of seconds simulated
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sim_ticks 1907689250500 # Number of ticks simulated
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system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu0.BPredUnit.BTBHits 5124021 # Number of BTB hits
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system.cpu0.BPredUnit.BTBLookups 9548324 # Number of BTB lookups
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system.cpu0.BPredUnit.RASInCorrect 25931 # Number of incorrect RAS predictions.
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system.cpu0.BPredUnit.condIncorrect 576265 # Number of conditional branches incorrect
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system.cpu0.BPredUnit.condPredicted 8953132 # Number of conditional branches predicted
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system.cpu0.BPredUnit.lookups 10665388 # Number of BP lookups
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system.cpu0.BPredUnit.usedRAS 730260 # Number of times the RAS was used to get a target.
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system.cpu0.commit.COM:branches 6306789 # Number of branches committed
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system.cpu0.commit.COM:bw_lim_events 727470 # number cycles where commit BW limit reached
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system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu0.commit.COM:committed_per_cycle::samples 73665183 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::mean 0.571097 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::stdev 1.330919 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::0 55454240 75.28% 75.28% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::1 8064036 10.95% 86.23% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::2 4660922 6.33% 92.55% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::3 2129949 2.89% 95.44% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::4 1559149 2.12% 97.56% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::5 477103 0.65% 98.21% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::6 293859 0.40% 98.61% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::7 298455 0.41% 99.01% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::8 727470 0.99% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu0.commit.COM:committed_per_cycle::total 73665183 # Number of insts commited each cycle
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system.cpu0.commit.COM:count 42069937 # Number of instructions committed
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system.cpu0.commit.COM:loads 6784715 # Number of loads committed
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system.cpu0.commit.COM:membars 161083 # Number of memory barriers committed
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system.cpu0.commit.COM:refs 11506692 # Number of memory references committed
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system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu0.commit.branchMispredicts 548150 # The number of times a branch was mispredicted
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system.cpu0.commit.commitCommittedInsts 42069937 # The number of committed instructions
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system.cpu0.commit.commitNonSpecStalls 486094 # The number of times commit has been forced to stall to communicate backwards
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system.cpu0.commit.commitSquashedInsts 6570892 # The number of squashed insts skipped by commit
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system.cpu0.committedInsts 39732534 # Number of Instructions Simulated
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system.cpu0.committedInsts_total 39732534 # Number of Instructions Simulated
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system.cpu0.cpi 2.659989 # CPI: Cycles Per Instruction
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system.cpu0.cpi_total 2.659989 # CPI: Total CPI of All Threads
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system.cpu0.dcache.LoadLockedReq_accesses::0 157022 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_accesses::total 157022 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15337.494650 # average LoadLockedReq miss latency
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system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11734.631539 # average LoadLockedReq mshr miss latency
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system.cpu0.dcache.LoadLockedReq_hits::0 143004 # number of LoadLockedReq hits
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system.cpu0.dcache.LoadLockedReq_hits::total 143004 # number of LoadLockedReq hits
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system.cpu0.dcache.LoadLockedReq_miss_latency 215001000 # number of LoadLockedReq miss cycles
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system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.089274 # miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_misses::0 14018 # number of LoadLockedReq misses
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system.cpu0.dcache.LoadLockedReq_misses::total 14018 # number of LoadLockedReq misses
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system.cpu0.dcache.LoadLockedReq_mshr_hits 3542 # number of LoadLockedReq MSHR hits
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system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 122932000 # number of LoadLockedReq MSHR miss cycles
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.066717 # mshr miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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system.cpu0.dcache.LoadLockedReq_mshr_misses 10476 # number of LoadLockedReq MSHR misses
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system.cpu0.dcache.ReadReq_accesses::0 6796922 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_accesses::total 6796922 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_avg_miss_latency::0 28045.834026 # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27628.067292 # average ReadReq mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.ReadReq_hits::0 5780701 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_hits::total 5780701 # number of ReadReq hits
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system.cpu0.dcache.ReadReq_miss_latency 28500765500 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate::0 0.149512 # miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_misses::0 1016221 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_misses::total 1016221 # number of ReadReq misses
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system.cpu0.dcache.ReadReq_mshr_hits 272772 # number of ReadReq MSHR hits
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system.cpu0.dcache.ReadReq_mshr_miss_latency 20540059000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109380 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.ReadReq_mshr_misses 743449 # number of ReadReq MSHR misses
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system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639143000 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.dcache.StoreCondReq_accesses::0 165236 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_accesses::total 165236 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54890.406800 # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51890.406800 # average StoreCondReq mshr miss latency
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system.cpu0.dcache.StoreCondReq_hits::0 147119 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 147119 # number of StoreCondReq hits
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system.cpu0.dcache.StoreCondReq_miss_latency 994449500 # number of StoreCondReq miss cycles
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system.cpu0.dcache.StoreCondReq_miss_rate::0 0.109643 # miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_misses::0 18117 # number of StoreCondReq misses
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system.cpu0.dcache.StoreCondReq_misses::total 18117 # number of StoreCondReq misses
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system.cpu0.dcache.StoreCondReq_mshr_miss_latency 940098500 # number of StoreCondReq MSHR miss cycles
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.109643 # mshr miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_mshr_misses 18117 # number of StoreCondReq MSHR misses
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system.cpu0.dcache.WriteReq_accesses::0 4544003 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 4544003 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_avg_miss_latency::0 48917.848661 # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54316.339615 # average WriteReq mshr miss latency
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu0.dcache.WriteReq_hits::0 2781940 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 2781940 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_miss_latency 86196331165 # number of WriteReq miss cycles
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system.cpu0.dcache.WriteReq_miss_rate::0 0.387778 # miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_misses::0 1762063 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_misses::total 1762063 # number of WriteReq misses
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system.cpu0.dcache.WriteReq_mshr_hits 1458631 # number of WriteReq MSHR hits
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system.cpu0.dcache.WriteReq_mshr_miss_latency 16481315562 # number of WriteReq MSHR miss cycles
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system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066776 # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.WriteReq_mshr_misses 303432 # number of WriteReq MSHR misses
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system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1049908497 # number of WriteReq MSHR uncacheable cycles
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9537.404034 # average number of cycles each access was blocked
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system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu0.dcache.avg_refs 9.143990 # Average number of references to valid blocks.
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system.cpu0.dcache.blocked::no_mshrs 120871 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_mshrs 1152795563 # number of cycles access was blocked
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.demand_accesses::0 11340925 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 11340925 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_avg_miss_latency::0 41283.431307 # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu0.dcache.demand_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency
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system.cpu0.dcache.demand_hits::0 8562641 # number of demand (read+write) hits
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system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
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system.cpu0.dcache.demand_hits::total 8562641 # number of demand (read+write) hits
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system.cpu0.dcache.demand_miss_latency 114697096665 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_miss_rate::0 0.244979 # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu0.dcache.demand_misses::0 2778284 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu0.dcache.demand_misses::total 2778284 # number of demand (read+write) misses
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system.cpu0.dcache.demand_mshr_hits 1731403 # number of demand (read+write) MSHR hits
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system.cpu0.dcache.demand_mshr_miss_latency 37021374562 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.demand_mshr_miss_rate::0 0.092310 # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu0.dcache.demand_mshr_misses 1046881 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.occ_%::0 0.870622 # Average percentage of cache occupancy
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system.cpu0.dcache.occ_blocks::0 445.758667 # Average occupied blocks per context
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system.cpu0.dcache.overall_accesses::0 11340925 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 11340925 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_avg_miss_latency::0 41283.431307 # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu0.dcache.overall_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu0.dcache.overall_hits::0 8562641 # number of overall hits
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system.cpu0.dcache.overall_hits::1 0 # number of overall hits
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system.cpu0.dcache.overall_hits::total 8562641 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 114697096665 # number of overall miss cycles
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system.cpu0.dcache.overall_miss_rate::0 0.244979 # miss rate for overall accesses
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|
system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu0.dcache.overall_misses::0 2778284 # number of overall misses
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system.cpu0.dcache.overall_misses::1 0 # number of overall misses
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system.cpu0.dcache.overall_misses::total 2778284 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 1731403 # number of overall MSHR hits
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system.cpu0.dcache.overall_mshr_miss_latency 37021374562 # number of overall MSHR miss cycles
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system.cpu0.dcache.overall_mshr_miss_rate::0 0.092310 # mshr miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_misses 1046881 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency 1689051497 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.replacements 987239 # number of replacements
|
|
system.cpu0.dcache.sampled_refs 987751 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu0.dcache.tagsinuse 445.758667 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 9031985 # Total number of references to valid blocks.
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|
system.cpu0.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit.
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|
system.cpu0.dcache.writebacks 319854 # number of writebacks
|
|
system.cpu0.decode.DECODE:BlockedCycles 35782513 # Number of cycles decode is blocked
|
|
system.cpu0.decode.DECODE:BranchMispred 28650 # Number of times decode detected a branch misprediction
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|
system.cpu0.decode.DECODE:BranchResolved 428056 # Number of times decode resolved a branch
|
|
system.cpu0.decode.DECODE:DecodedInsts 53705173 # Number of instructions handled by decode
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|
system.cpu0.decode.DECODE:IdleCycles 27333196 # Number of cycles decode is idle
|
|
system.cpu0.decode.DECODE:RunCycles 9585932 # Number of cycles decode is running
|
|
system.cpu0.decode.DECODE:SquashCycles 1147003 # Number of cycles decode is squashing
|
|
system.cpu0.decode.DECODE:SquashedInsts 91050 # Number of squashed instructions handled by decode
|
|
system.cpu0.decode.DECODE:UnblockCycles 963541 # Number of cycles decode is unblocking
|
|
system.cpu0.dtb.data_accesses 873282 # DTB accesses
|
|
system.cpu0.dtb.data_acv 817 # DTB access violations
|
|
system.cpu0.dtb.data_hits 12339819 # DTB hits
|
|
system.cpu0.dtb.data_misses 31654 # DTB misses
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.read_accesses 648811 # DTB read accesses
|
|
system.cpu0.dtb.read_acv 602 # DTB read access violations
|
|
system.cpu0.dtb.read_hits 7477600 # DTB read hits
|
|
system.cpu0.dtb.read_misses 25745 # DTB read misses
|
|
system.cpu0.dtb.write_accesses 224471 # DTB write accesses
|
|
system.cpu0.dtb.write_acv 215 # DTB write access violations
|
|
system.cpu0.dtb.write_hits 4862219 # DTB write hits
|
|
system.cpu0.dtb.write_misses 5909 # DTB write misses
|
|
system.cpu0.fetch.Branches 10665388 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.CacheLines 6760263 # Number of cache lines fetched
|
|
system.cpu0.fetch.Cycles 17500096 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.IcacheSquashes 314893 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.Insts 54825819 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.MiscStallCycles 926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.SquashCycles 690026 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.branchRate 0.100914 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.icacheStallCycles 6760263 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.predictedBranches 5854281 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.rate 0.518751 # Number of inst fetches per cycle
|
|
system.cpu0.fetch.rateDist::samples 74812186 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.732846 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.023907 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 64104390 85.69% 85.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 792685 1.06% 86.75% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 1475450 1.97% 88.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 663490 0.89% 89.61% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 2416214 3.23% 92.84% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 489674 0.65% 93.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 557514 0.75% 94.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 868698 1.16% 95.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 3444071 4.60% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 74812186 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.icache.ReadReq_accesses::0 6760263 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 6760263 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::0 15111.361670 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12055.592401 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_hits::0 6055842 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 6055842 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_miss_latency 10644760499 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_rate::0 0.104200 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_misses::0 704421 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 704421 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_mshr_hits 31973 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency 8106758999 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.099471 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_misses 672448 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11292.658537 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_refs 9.007622 # Average number of references to valid blocks.
|
|
system.cpu0.icache.blocked::no_mshrs 41 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 462999 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.demand_accesses::0 6760263 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 6760263 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_avg_miss_latency::0 15111.361670 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_hits::0 6055842 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 6055842 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_miss_latency 10644760499 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_rate::0 0.104200 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu0.icache.demand_misses::0 704421 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 704421 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_mshr_hits 31973 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_miss_latency 8106758999 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_rate::0 0.099471 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_misses 672448 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.occ_%::0 0.995774 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_blocks::0 509.836147 # Average occupied blocks per context
|
|
system.cpu0.icache.overall_accesses::0 6760263 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 6760263 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_avg_miss_latency::0 15111.361670 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_hits::0 6055842 # number of overall hits
|
|
system.cpu0.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 6055842 # number of overall hits
|
|
system.cpu0.icache.overall_miss_latency 10644760499 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_rate::0 0.104200 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu0.icache.overall_misses::0 704421 # number of overall misses
|
|
system.cpu0.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 704421 # number of overall misses
|
|
system.cpu0.icache.overall_mshr_hits 31973 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_miss_latency 8106758999 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_rate::0 0.099471 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_misses 672448 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu0.icache.replacements 671790 # number of replacements
|
|
system.cpu0.icache.sampled_refs 672302 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu0.icache.tagsinuse 509.836147 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 6055842 # Total number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 25289603000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.writebacks 0 # number of writebacks
|
|
system.cpu0.idleCycles 30875932 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.iew.EXEC:branches 6794464 # Number of branches executed
|
|
system.cpu0.iew.EXEC:nop 2650714 # number of nop insts executed
|
|
system.cpu0.iew.EXEC:rate 0.405657 # Inst execution rate
|
|
system.cpu0.iew.EXEC:refs 12475412 # number of memory reference insts executed
|
|
system.cpu0.iew.EXEC:stores 4878585 # Number of stores executed
|
|
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu0.iew.WB:consumers 25547065 # num instructions consuming a value
|
|
system.cpu0.iew.WB:count 42445288 # cumulative count of insts written-back
|
|
system.cpu0.iew.WB:fanout 0.775506 # average fanout of values written-back
|
|
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.iew.WB:producers 19811901 # num instructions producing a value
|
|
system.cpu0.iew.WB:rate 0.401609 # insts written-back per cycle
|
|
system.cpu0.iew.WB:sent 42518285 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.branchMispredicts 591859 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewBlockCycles 7490199 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewDispLoadInsts 8008916 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 1306307 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewDispSquashedInsts 773924 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispStoreInsts 5151785 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispatchedInsts 48752960 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewExecLoadInsts 7596827 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 385648 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.iewExecutedInsts 42873082 # Number of executed instructions
|
|
system.cpu0.iew.iewIQFullEvents 34285 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewLSQFullEvents 4894 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.iewSquashCycles 1147003 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewUnblockCycles 462624 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread.0.cacheBlocked 256589 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.lsq.thread.0.forwLoads 371728 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread.0.ignoredResponses 8138 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread.0.memOrderViolation 36722 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread.0.rescheduledLoads 12836 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread.0.squashedLoads 1224201 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread.0.squashedStores 429808 # Number of stores squashed
|
|
system.cpu0.iew.memOrderViolationEvents 36722 # Number of memory order violations
|
|
system.cpu0.iew.predictedNotTakenIncorrect 290524 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.predictedTakenIncorrect 301335 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.ipc 0.375941 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.375941 # IPC: Total IPC of All Threads
|
|
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 29744442 68.76% 68.77% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntMult 44172 0.10% 68.87% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.87% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 13702 0.03% 68.90% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.90% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.90% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.90% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1883 0.00% 68.91% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.91% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemRead 7844859 18.13% 87.04% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4914921 11.36% 98.40% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 690973 1.60% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.ISSUE:FU_type_0::total 43258732 # Type of FU issued
|
|
system.cpu0.iq.ISSUE:fu_busy_cnt 310534 # FU busy when requested
|
|
system.cpu0.iq.ISSUE:fu_busy_rate 0.007179 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntAlu 34104 10.98% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.98% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::MemRead 200961 64.71% 75.70% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::MemWrite 75469 24.30% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::samples 74812186 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.578231 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.135171 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::0 52955077 70.78% 70.78% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::1 11074556 14.80% 85.59% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::2 4848896 6.48% 92.07% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::3 2948908 3.94% 96.01% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::4 1827398 2.44% 98.45% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::5 727506 0.97% 99.43% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::6 332197 0.44% 99.87% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::7 81828 0.11% 99.98% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::8 15820 0.02% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:issued_per_cycle::total 74812186 # Number of insts issued each cycle
|
|
system.cpu0.iq.ISSUE:rate 0.409306 # Inst issue rate
|
|
system.cpu0.iq.iqInstsAdded 44617182 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqInstsIssued 43258732 # Number of instructions issued
|
|
system.cpu0.iq.iqNonSpecInstsAdded 1485064 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqSquashedInstsExamined 6087251 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedInstsIssued 24441 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 998970 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.iqSquashedOperandsExamined 3229124 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.fetch_accesses 930014 # ITB accesses
|
|
system.cpu0.itb.fetch_acv 893 # ITB acv
|
|
system.cpu0.itb.fetch_hits 898869 # ITB hits
|
|
system.cpu0.itb.fetch_misses 31145 # ITB misses
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wripir 96 0.07% 0.07% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 2652 1.92% 1.99% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 51 0.04% 2.03% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.01% 2.04% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 124030 89.84% 91.88% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6358 4.61% 96.48% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.48% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 4 0.00% 96.49% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 9 0.01% 96.49% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.50% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 4305 3.12% 99.61% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 394 0.29% 99.90% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 139 0.10% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 138052 # number of callpals executed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.hwrei 153418 # number of hwrei instructions executed
|
|
system.cpu0.kern.inst.quiesce 4853 # number of quiesce instructions executed
|
|
system.cpu0.kern.ipl_count::0 51417 39.39% 39.39% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 237 0.18% 39.58% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1931 1.48% 41.06% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::30 16 0.01% 41.07% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 76919 58.93% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 130520 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 50665 48.95% 48.95% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 237 0.23% 49.18% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1931 1.87% 51.05% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::30 16 0.02% 51.06% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 50649 48.94% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 103498 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1871325988500 98.09% 98.09% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 101211000 0.01% 98.10% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 398014500 0.02% 98.12% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::30 8513500 0.00% 98.12% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 35854604500 1.88% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1907688332000 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.985374 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.658472 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.mode_good::kernel 1370
|
|
system.cpu0.kern.mode_good::user 1371
|
|
system.cpu0.kern.mode_good::idle 0
|
|
system.cpu0.kern.mode_switch::kernel 6220 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch_good::kernel 0.220257 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 1905422249500 99.88% 99.88% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 2266074500 0.12% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 2653 # number of times the context was actually changed
|
|
system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 234 # number of syscalls executed
|
|
system.cpu0.memDep0.conflictingLoads 2188476 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 1997712 # Number of conflicting stores.
|
|
system.cpu0.memDep0.insertedLoads 8008916 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 5151785 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.numCycles 105688118 # number of cpu cycles simulated
|
|
system.cpu0.rename.RENAME:BlockCycles 11112209 # Number of cycles rename is blocking
|
|
system.cpu0.rename.RENAME:CommittedMaps 28779848 # Number of HB maps that are committed
|
|
system.cpu0.rename.RENAME:IQFullEvents 792454 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.RENAME:IdleCycles 28590888 # Number of cycles rename is idle
|
|
system.cpu0.rename.RENAME:LSQFullEvents 1753238 # Number of times rename has blocked due to LSQ full
|
|
system.cpu0.rename.RENAME:ROBFullEvents 16675 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.RENAME:RenameLookups 62049686 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.RENAME:RenamedInsts 50763826 # Number of instructions processed by rename
|
|
system.cpu0.rename.RENAME:RenamedOperands 34216131 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RENAME:RunCycles 9514762 # Number of cycles rename is running
|
|
system.cpu0.rename.RENAME:SquashCycles 1147003 # Number of cycles rename is squashing
|
|
system.cpu0.rename.RENAME:UnblockCycles 3857610 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RENAME:UndoneMaps 5436281 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.RENAME:serializeStallCycles 20589712 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RENAME:serializingInsts 1236784 # count of serializing insts renamed
|
|
system.cpu0.rename.RENAME:skidInsts 9152277 # count of insts added to the skid buffer
|
|
system.cpu0.rename.RENAME:tempSerializingInsts 192000 # count of temporary serializing insts renamed
|
|
system.cpu0.timesIdled 961954 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.BPredUnit.BTBHits 1953599 # Number of BTB hits
|
|
system.cpu1.BPredUnit.BTBLookups 4355656 # Number of BTB lookups
|
|
system.cpu1.BPredUnit.RASInCorrect 14923 # Number of incorrect RAS predictions.
|
|
system.cpu1.BPredUnit.condIncorrect 286606 # Number of conditional branches incorrect
|
|
system.cpu1.BPredUnit.condPredicted 4049478 # Number of conditional branches predicted
|
|
system.cpu1.BPredUnit.lookups 4938226 # Number of BP lookups
|
|
system.cpu1.BPredUnit.usedRAS 376891 # Number of times the RAS was used to get a target.
|
|
system.cpu1.commit.COM:branches 2617539 # Number of branches committed
|
|
system.cpu1.commit.COM:bw_lim_events 356362 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.commit.COM:committed_per_cycle::samples 33118489 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::mean 0.526612 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::stdev 1.338198 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::0 25969028 78.41% 78.41% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::1 3179753 9.60% 88.01% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::2 1522948 4.60% 92.61% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::3 936064 2.83% 95.44% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::4 628296 1.90% 97.34% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::5 237537 0.72% 98.05% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::6 164527 0.50% 98.55% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::7 123974 0.37% 98.92% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::8 356362 1.08% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:committed_per_cycle::total 33118489 # Number of insts commited each cycle
|
|
system.cpu1.commit.COM:count 17440586 # Number of instructions committed
|
|
system.cpu1.commit.COM:loads 3166581 # Number of loads committed
|
|
system.cpu1.commit.COM:membars 77258 # Number of memory barriers committed
|
|
system.cpu1.commit.COM:refs 5179825 # Number of memory references committed
|
|
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.branchMispredicts 272102 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.commitCommittedInsts 17440586 # The number of committed instructions
|
|
system.cpu1.commit.commitNonSpecStalls 227930 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.commitSquashedInsts 3329840 # The number of squashed insts skipped by commit
|
|
system.cpu1.committedInsts 16438996 # Number of Instructions Simulated
|
|
system.cpu1.committedInsts_total 16438996 # Number of Instructions Simulated
|
|
system.cpu1.cpi 2.304097 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 2.304097 # CPI: Total CPI of All Threads
|
|
system.cpu1.dcache.LoadLockedReq_accesses::0 63271 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 63271 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14821.069300 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11124.971610 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_hits::0 52535 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 52535 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency 159119000 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.169683 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_misses::0 10736 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 10736 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits 1930 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97966500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.139179 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses 8806 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_accesses::0 3203716 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 3203716 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::0 15842.853412 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12100.517465 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_hits::0 2644617 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 2644617 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_miss_latency 8857723500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_rate::0 0.174516 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_misses::0 559099 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 559099 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_mshr_hits 185547 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency 4520172500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.116600 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_misses 373552 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298583500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.StoreCondReq_accesses::0 59498 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 59498 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54415.622389 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51415.622389 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_hits::0 45134 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 45134 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_miss_latency 781626000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::0 0.241420 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_misses::0 14364 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 14364 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency 738534000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.241420 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses 14364 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_accesses::0 1946502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 1946502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::0 49498.272766 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54160.909528 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_hits::0 1381655 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 1381655 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_miss_latency 27958950877 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_rate::0 0.290186 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_misses::0 564847 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 564847 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_mshr_hits 446490 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency 6410322769 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.060805 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_misses 118357 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526362000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13351.888091 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_refs 9.264017 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.blocked::no_mshrs 24797 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 331086769 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 18500 # number of cycles access was blocked
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.demand_accesses::0 5150218 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 5150218 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_avg_miss_latency::0 32756.622095 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_hits::0 4026272 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 4026272 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_miss_latency 36816674377 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_rate::0 0.218233 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_misses::0 1123946 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 1123946 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_mshr_hits 632037 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_miss_latency 10930495269 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_rate::0 0.095512 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_misses 491909 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.occ_%::0 0.951616 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_blocks::0 487.227171 # Average occupied blocks per context
|
|
system.cpu1.dcache.overall_accesses::0 5150218 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 5150218 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_avg_miss_latency::0 32756.622095 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_hits::0 4026272 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::1 0 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 4026272 # number of overall hits
|
|
system.cpu1.dcache.overall_miss_latency 36816674377 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_rate::0 0.218233 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_misses::0 1123946 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::1 0 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 1123946 # number of overall misses
|
|
system.cpu1.dcache.overall_mshr_hits 632037 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_miss_latency 10930495269 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_rate::0 0.095512 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_misses 491909 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency 824945500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.replacements 455363 # number of replacements
|
|
system.cpu1.dcache.sampled_refs 455691 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.dcache.tagsinuse 487.227171 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 4221529 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 41371153000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.writebacks 131807 # number of writebacks
|
|
system.cpu1.decode.DECODE:BlockedCycles 15690044 # Number of cycles decode is blocked
|
|
system.cpu1.decode.DECODE:BranchMispred 15658 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DECODE:BranchResolved 221514 # Number of times decode resolved a branch
|
|
system.cpu1.decode.DECODE:DecodedInsts 23293804 # Number of instructions handled by decode
|
|
system.cpu1.decode.DECODE:IdleCycles 13052984 # Number of cycles decode is idle
|
|
system.cpu1.decode.DECODE:RunCycles 4174567 # Number of cycles decode is running
|
|
system.cpu1.decode.DECODE:SquashCycles 566096 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DECODE:SquashedInsts 47077 # Number of squashed instructions handled by decode
|
|
system.cpu1.decode.DECODE:UnblockCycles 200893 # Number of cycles decode is unblocking
|
|
system.cpu1.dtb.data_accesses 379955 # DTB accesses
|
|
system.cpu1.dtb.data_acv 65 # DTB access violations
|
|
system.cpu1.dtb.data_hits 5542909 # DTB hits
|
|
system.cpu1.dtb.data_misses 13981 # DTB misses
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.read_accesses 276518 # DTB read accesses
|
|
system.cpu1.dtb.read_acv 12 # DTB read access violations
|
|
system.cpu1.dtb.read_hits 3445692 # DTB read hits
|
|
system.cpu1.dtb.read_misses 11718 # DTB read misses
|
|
system.cpu1.dtb.write_accesses 103437 # DTB write accesses
|
|
system.cpu1.dtb.write_acv 53 # DTB write access violations
|
|
system.cpu1.dtb.write_hits 2097217 # DTB write hits
|
|
system.cpu1.dtb.write_misses 2263 # DTB write misses
|
|
system.cpu1.fetch.Branches 4938226 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.CacheLines 2741713 # Number of cache lines fetched
|
|
system.cpu1.fetch.Cycles 7194016 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.IcacheSquashes 172775 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.Insts 23780795 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.MiscStallCycles 714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.SquashCycles 326197 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.branchRate 0.130375 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.icacheStallCycles 2741713 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.predictedBranches 2330490 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.rate 0.627842 # Number of inst fetches per cycle
|
|
system.cpu1.fetch.rateDist::samples 33684585 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 0.705985 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.028331 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 29238127 86.80% 86.80% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 297283 0.88% 87.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 597287 1.77% 89.46% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 350001 1.04% 90.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 693611 2.06% 92.55% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 228580 0.68% 93.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 280979 0.83% 94.07% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 354019 1.05% 95.12% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 1644698 4.88% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 33684585 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.icache.ReadReq_accesses::0 2741713 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 2741713 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::0 14618.155893 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11660.018500 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_hits::0 2328949 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 2328949 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_miss_latency 6033848499 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_rate::0 0.150550 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_misses::0 412764 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 412764 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_mshr_hits 18169 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency 4600985000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143923 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_misses 394595 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 11340.909091 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_refs 5.902933 # Average number of references to valid blocks.
|
|
system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 249500 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.demand_accesses::0 2741713 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 2741713 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_avg_miss_latency::0 14618.155893 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_hits::0 2328949 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 2328949 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_miss_latency 6033848499 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_rate::0 0.150550 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.cpu1.icache.demand_misses::0 412764 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 412764 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_mshr_hits 18169 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_miss_latency 4600985000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_rate::0 0.143923 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_misses 394595 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.occ_%::0 0.984930 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_blocks::0 504.284109 # Average occupied blocks per context
|
|
system.cpu1.icache.overall_accesses::0 2741713 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 2741713 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_avg_miss_latency::0 14618.155893 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_hits::0 2328949 # number of overall hits
|
|
system.cpu1.icache.overall_hits::1 0 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 2328949 # number of overall hits
|
|
system.cpu1.icache.overall_miss_latency 6033848499 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_rate::0 0.150550 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.cpu1.icache.overall_misses::0 412764 # number of overall misses
|
|
system.cpu1.icache.overall_misses::1 0 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 412764 # number of overall misses
|
|
system.cpu1.icache.overall_mshr_hits 18169 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_miss_latency 4600985000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_rate::0 0.143923 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_misses 394595 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu1.icache.replacements 394030 # number of replacements
|
|
system.cpu1.icache.sampled_refs 394541 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu1.icache.tagsinuse 504.284109 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 2328949 # Total number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 54145022000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.writebacks 0 # number of writebacks
|
|
system.cpu1.idleCycles 4192462 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.iew.EXEC:branches 2856676 # Number of branches executed
|
|
system.cpu1.iew.EXEC:nop 1154303 # number of nop insts executed
|
|
system.cpu1.iew.EXEC:rate 0.475940 # Inst execution rate
|
|
system.cpu1.iew.EXEC:refs 5695199 # number of memory reference insts executed
|
|
system.cpu1.iew.EXEC:stores 2106410 # Number of stores executed
|
|
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
|
|
system.cpu1.iew.WB:consumers 11059026 # num instructions consuming a value
|
|
system.cpu1.iew.WB:count 17811363 # cumulative count of insts written-back
|
|
system.cpu1.iew.WB:fanout 0.729393 # average fanout of values written-back
|
|
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.iew.WB:producers 8066373 # num instructions producing a value
|
|
system.cpu1.iew.WB:rate 0.470242 # insts written-back per cycle
|
|
system.cpu1.iew.WB:sent 17846809 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.branchMispredicts 295481 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewBlockCycles 2247167 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewDispLoadInsts 3784809 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 705322 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewDispSquashedInsts 304722 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispStoreInsts 2229881 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispatchedInsts 20840957 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewExecLoadInsts 3588789 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 201614 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.iewExecutedInsts 18027204 # Number of executed instructions
|
|
system.cpu1.iew.iewIQFullEvents 12484 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewLSQFullEvents 2361 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.iewSquashCycles 566096 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewUnblockCycles 83136 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread.0.cacheBlocked 73212 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.lsq.thread.0.forwLoads 122514 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread.0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread.0.memOrderViolation 16678 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread.0.rescheduledLoads 6458 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread.0.squashedLoads 618228 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread.0.squashedStores 216637 # Number of stores squashed
|
|
system.cpu1.iew.memOrderViolationEvents 16678 # Number of memory order violations
|
|
system.cpu1.iew.predictedNotTakenIncorrect 152685 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.predictedTakenIncorrect 142796 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.ipc 0.434009 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.434009 # IPC: Total IPC of All Threads
|
|
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3528 0.02% 0.02% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 11967153 65.65% 65.67% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntMult 27009 0.15% 65.82% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.82% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 12064 0.07% 65.88% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.01% 65.89% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.89% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemRead 3711124 20.36% 86.25% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2127008 11.67% 97.92% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 379173 2.08% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.ISSUE:FU_type_0::total 18228818 # Type of FU issued
|
|
system.cpu1.iq.ISSUE:fu_busy_cnt 196946 # FU busy when requested
|
|
system.cpu1.iq.ISSUE:fu_busy_rate 0.010804 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntAlu 13962 7.09% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.09% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::MemRead 116519 59.16% 66.25% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::MemWrite 66465 33.75% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::samples 33684585 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.541162 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.162170 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::0 25088136 74.48% 74.48% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::1 4124812 12.25% 86.72% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::2 1756786 5.22% 91.94% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::3 1209447 3.59% 95.53% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::4 865609 2.57% 98.10% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::5 413218 1.23% 99.33% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::6 164057 0.49% 99.81% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::7 50935 0.15% 99.97% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::8 11585 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:issued_per_cycle::total 33684585 # Number of insts issued each cycle
|
|
system.cpu1.iq.ISSUE:rate 0.481263 # Inst issue rate
|
|
system.cpu1.iq.iqInstsAdded 18897687 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqInstsIssued 18228818 # Number of instructions issued
|
|
system.cpu1.iq.iqNonSpecInstsAdded 788967 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqSquashedInstsExamined 3125649 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedInstsIssued 15583 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 561037 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.iqSquashedOperandsExamined 1602623 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.fetch_accesses 472041 # ITB accesses
|
|
system.cpu1.itb.fetch_acv 106 # ITB acv
|
|
system.cpu1.itb.fetch_hits 466299 # ITB hits
|
|
system.cpu1.itb.fetch_misses 5742 # ITB misses
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 1586 2.01% 2.04% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 3 0.00% 2.04% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 2.05% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 71639 90.87% 92.92% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2407 3.05% 95.97% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 95.97% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 3 0.00% 95.97% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.00% 95.98% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 3007 3.81% 99.79% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 121 0.15% 99.95% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 78839 # number of callpals executed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.hwrei 84815 # number of hwrei instructions executed
|
|
system.cpu1.kern.inst.quiesce 3812 # number of quiesce instructions executed
|
|
system.cpu1.kern.ipl_count::0 30474 39.75% 39.75% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1928 2.51% 42.26% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 96 0.13% 42.39% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 44173 57.61% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 76671 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 29849 48.44% 48.44% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1928 3.13% 51.56% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 96 0.16% 51.72% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 29753 48.28% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 61626 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1872267971000 98.16% 98.16% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 351911000 0.02% 98.18% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 40319500 0.00% 98.19% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 34610873000 1.81% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1907271074500 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.979491 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.673556 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.mode_good::kernel 424
|
|
system.cpu1.kern.mode_good::user 366
|
|
system.cpu1.kern.mode_good::idle 58
|
|
system.cpu1.kern.mode_switch::kernel 1953 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 366 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch_good::kernel 0.217102 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.028473 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 1.245575 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 44394454000 2.33% 2.33% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 886105500 0.05% 2.37% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1861549295500 97.63% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 1587 # number of times the context was actually changed
|
|
system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
|
|
system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
|
|
system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
|
|
system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
|
|
system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
|
|
system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
|
|
system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
|
|
system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
|
|
system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
|
|
system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
|
|
system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
|
|
system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
|
|
system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::total 92 # number of syscalls executed
|
|
system.cpu1.memDep0.conflictingLoads 820507 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 719564 # Number of conflicting stores.
|
|
system.cpu1.memDep0.insertedLoads 3784809 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 2229881 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.numCycles 37877047 # number of cpu cycles simulated
|
|
system.cpu1.rename.RENAME:BlockCycles 3238650 # Number of cycles rename is blocking
|
|
system.cpu1.rename.RENAME:CommittedMaps 11736980 # Number of HB maps that are committed
|
|
system.cpu1.rename.RENAME:IQFullEvents 293624 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.RENAME:IdleCycles 13473240 # Number of cycles rename is idle
|
|
system.cpu1.rename.RENAME:LSQFullEvents 554151 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.RENAME:ROBFullEvents 942 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.RENAME:RenameLookups 26045586 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.RENAME:RenamedInsts 21738411 # Number of instructions processed by rename
|
|
system.cpu1.rename.RENAME:RenamedOperands 14384581 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RENAME:RunCycles 3820320 # Number of cycles rename is running
|
|
system.cpu1.rename.RENAME:SquashCycles 566096 # Number of cycles rename is squashing
|
|
system.cpu1.rename.RENAME:UnblockCycles 1590671 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RENAME:UndoneMaps 2647601 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.RENAME:serializeStallCycles 10995606 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RENAME:serializingInsts 652471 # count of serializing insts renamed
|
|
system.cpu1.rename.RENAME:skidInsts 4381532 # count of insts added to the skid buffer
|
|
system.cpu1.rename.RENAME:tempSerializingInsts 75403 # count of temporary serializing insts renamed
|
|
system.cpu1.timesIdled 422616 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::1 115252.862069 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63252.862069 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_miss_latency 20053998 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses::1 174 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
|
system.iocache.ReadReq_mshr_miss_latency 11005998 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::1 137849.677657 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85846.237437 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_miss_latency 5727929806 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_mshr_miss_latency 3567082858 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6166.374068 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_mshrs 64487940 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::1 137755.447539 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 5747983804 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 41726 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 3578088856 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.occ_%::1 0.028124 # Average percentage of cache occupancy
|
|
system.iocache.occ_blocks::1 0.449991 # Average occupied blocks per context
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 137755.447539 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 5747983804 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 41726 # number of overall misses
|
|
system.iocache.overall_misses::total 41726 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 3578088856 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 41696 # number of replacements
|
|
system.iocache.sampled_refs 41712 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 0.449991 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1717168496000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 41522 # number of writebacks
|
|
system.l2c.ReadExReq_accesses::0 236243 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::1 78291 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 314534 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency::0 69731.847293 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::1 210415.766819 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40217.604332 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_miss_latency 16473660800 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 236243 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::1 78291 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 314534 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 12649803961 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 1.331400 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 4.017499 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 314534 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses::0 1423603 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::1 771316 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2194919 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency::0 53400.832785 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::1 1985457.471546 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 39990.811057 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits::0 1119803 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::1 763145 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1882948 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 16223173000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate::0 0.213402 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::1 0.010594 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 303800 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::1 8171 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 311971 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 12475173500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.219128 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::1 0.404440 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 311951 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 839822000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.SCUpgradeReq_accesses::0 17600 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::1 13825 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 31425 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::0 92935.170455 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::1 118311.681736 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40007.112172 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_miss_latency 1635659000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_misses::0 17600 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::1 13825 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 31425 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency 1257223500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.785511 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::1 2.273056 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_misses 31425 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_accesses::0 68860 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::1 40587 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 109447 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 80683.066918 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 136887.081775 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40119.011942 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_miss_latency 5555835988 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 68860 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::1 40587 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 109447 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 4390905500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 1.589413 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 2.696602 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 109447 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1423289998 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses::0 451661 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 451661 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 451661 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 451661 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 4.797703 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 1659846 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 849607 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2509453 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 60544.871057 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 378164.208554 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 1119803 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 763145 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1882948 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 32696833800 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.325357 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 0.101767 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 540043 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 86462 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 626505 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 20 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 25124977461 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0.377436 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 0.737382 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 626485 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_%::0 0.066802 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::1 0.029576 # Average percentage of cache occupancy
|
|
system.l2c.occ_%::2 0.372873 # Average percentage of cache occupancy
|
|
system.l2c.occ_blocks::0 4377.904620 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 1938.298251 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::2 24436.623036 # Average occupied blocks per context
|
|
system.l2c.overall_accesses::0 1659846 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 849607 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2509453 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 60544.871057 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 378164.208554 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 1119803 # number of overall hits
|
|
system.l2c.overall_hits::1 763145 # number of overall hits
|
|
system.l2c.overall_hits::2 0 # number of overall hits
|
|
system.l2c.overall_hits::total 1882948 # number of overall hits
|
|
system.l2c.overall_miss_latency 32696833800 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.325357 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 0.101767 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 540043 # number of overall misses
|
|
system.l2c.overall_misses::1 86462 # number of overall misses
|
|
system.l2c.overall_misses::2 0 # number of overall misses
|
|
system.l2c.overall_misses::total 626505 # number of overall misses
|
|
system.l2c.overall_mshr_hits 20 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 25124977461 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0.377436 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 0.737382 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 626485 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 2263111998 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 402176 # number of replacements
|
|
system.l2c.sampled_refs 435074 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 30752.825907 # Cycle average of tags in use
|
|
system.l2c.total_refs 2087356 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 9278644000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 124146 # number of writebacks
|
|
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
---------- End Simulation Statistics ----------
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