gem5/src
Nilay Vaish 7e27860ef4 ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus
directly.  Therefore the packets between the io devices and the interrupt
controller do not go through ruby.  This patch changes ruby port so that
these packets arrive at the ruby port first, which then routes them to their
destination.  Note that the patch does not make these packets go through the
ruby network.  That would happen in a subsequent patch.
2014-02-23 19:16:16 -06:00
..
arch x86: Fix x87 state transfer bug 2014-02-05 14:08:13 +01:00
base base: calls abort() from fatal 2014-02-06 16:30:13 -06:00
cpu kvm: Add support for multi-system simulation 2014-02-20 15:43:53 +01:00
dev dev: Include basic devices in NULL ISA build 2014-02-18 05:50:59 -05:00
doc MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern sim: Add openat/fstatat syscalls and fix mremap 2014-01-24 15:29:30 -06:00
mem ruby: route all packets through ruby port 2014-02-23 19:16:16 -06:00
proto base: Avoid size limitation on protobuf coded streams 2013-05-30 12:53:53 -04:00
python base: add support for probe points and common probes 2014-01-24 15:29:30 -06:00
sim arm: Add support for ARMv8 (AArch64 & AArch32) 2014-01-24 15:29:34 -06:00
unittest unittest: Fix build errors 2014-01-30 12:21:58 -06:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript cpu: allow the fetch buffer to be smaller than a cache line 2013-11-15 13:21:15 -05:00