433 lines
16 KiB
C++
433 lines
16 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cassert>
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#include "debug/RubyNetwork.hh"
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#include "mem/protocol/MachineType.hh"
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#include "mem/protocol/TopologyType.hh"
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#include "mem/ruby/common/NetDest.hh"
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#include "mem/ruby/network/BasicLink.hh"
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#include "mem/ruby/network/BasicRouter.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/network/Topology.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/system/System.hh"
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using namespace std;
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const int INFINITE_LATENCY = 10000; // Yes, this is a big hack
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class BasicRouter;
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// Note: In this file, we use the first 2*m_nodes SwitchIDs to
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// represent the input and output endpoint links. These really are
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// not 'switches', as they will not have a Switch object allocated for
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// them. The first m_nodes SwitchIDs are the links into the network,
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// the second m_nodes set of SwitchIDs represent the the output queues
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// of the network.
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// Helper functions based on chapter 29 of Cormen et al.
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void extend_shortest_path(Matrix& current_dist, Matrix& latencies,
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Matrix& inter_switches);
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Matrix shortest_path(const Matrix& weights, Matrix& latencies,
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Matrix& inter_switches);
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bool link_is_shortest_path_to_node(SwitchID src, SwitchID next,
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SwitchID final, const Matrix& weights, const Matrix& dist);
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NetDest shortest_path_to_node(SwitchID src, SwitchID next,
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const Matrix& weights, const Matrix& dist);
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Topology::Topology(const Params *p)
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: SimObject(p)
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{
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m_print_config = p->print_config;
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m_number_of_switches = p->routers.size();
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// initialize component latencies record
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m_component_latencies.resize(0);
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m_component_inter_switches.resize(0);
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// Total nodes/controllers in network
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// Must make sure this is called after the State Machine constructors
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m_nodes = MachineType_base_number(MachineType_NUM);
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assert(m_nodes > 1);
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if (m_nodes != params()->ext_links.size() &&
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m_nodes != params()->ext_links.size()) {
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fatal("m_nodes (%d) != ext_links vector length (%d)\n",
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m_nodes != params()->ext_links.size());
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}
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// analyze both the internal and external links, create data structures
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// Note that the python created links are bi-directional, but that the
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// topology and networks utilize uni-directional links. Thus each
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// BasicLink is converted to two calls to add link, on for each direction
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for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
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i != params()->ext_links.end(); ++i) {
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BasicExtLink *ext_link = (*i);
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AbstractController *abs_cntrl = ext_link->params()->ext_node;
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BasicRouter *router = ext_link->params()->int_node;
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// Store the controller and ExtLink pointers for later
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m_controller_vector.push_back(abs_cntrl);
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m_ext_link_vector.push_back(ext_link);
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int ext_idx1 = abs_cntrl->params()->cntrl_id;
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int ext_idx2 = ext_idx1 + m_nodes;
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int int_idx = router->params()->router_id + 2*m_nodes;
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// create the internal uni-directional links in both directions
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// the first direction is marked: In
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addLink(ext_idx1, int_idx, ext_link, LinkDirection_In);
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// the first direction is marked: Out
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addLink(int_idx, ext_idx2, ext_link, LinkDirection_Out);
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}
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for (vector<BasicIntLink*>::const_iterator i = params()->int_links.begin();
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i != params()->int_links.end(); ++i) {
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BasicIntLink *int_link = (*i);
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BasicRouter *router_a = int_link->params()->node_a;
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BasicRouter *router_b = int_link->params()->node_b;
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// Store the IntLink pointers for later
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m_int_link_vector.push_back(int_link);
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int a = router_a->params()->router_id + 2*m_nodes;
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int b = router_b->params()->router_id + 2*m_nodes;
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// create the internal uni-directional links in both directions
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// the first direction is marked: In
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addLink(a, b, int_link, LinkDirection_In);
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// the second direction is marked: Out
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addLink(b, a, int_link, LinkDirection_Out);
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}
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}
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void
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Topology::init()
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{
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}
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void
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Topology::initNetworkPtr(Network* net_ptr)
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{
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for (vector<BasicExtLink*>::const_iterator i = params()->ext_links.begin();
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i != params()->ext_links.end(); ++i) {
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BasicExtLink *ext_link = (*i);
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AbstractController *abs_cntrl = ext_link->params()->ext_node;
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abs_cntrl->initNetworkPtr(net_ptr);
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}
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}
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void
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Topology::createLinks(Network *net, bool isReconfiguration)
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{
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// Find maximum switchID
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SwitchID max_switch_id = 0;
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for (LinkMap::const_iterator i = m_link_map.begin();
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i != m_link_map.end(); ++i) {
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std::pair<int, int> src_dest = (*i).first;
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max_switch_id = max(max_switch_id, src_dest.first);
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max_switch_id = max(max_switch_id, src_dest.second);
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}
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// Initialize weight, latency, and inter switched vectors
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Matrix topology_weights;
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int num_switches = max_switch_id+1;
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topology_weights.resize(num_switches);
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m_component_latencies.resize(num_switches);
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m_component_inter_switches.resize(num_switches);
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for (int i = 0; i < topology_weights.size(); i++) {
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topology_weights[i].resize(num_switches);
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m_component_latencies[i].resize(num_switches);
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m_component_inter_switches[i].resize(num_switches);
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for (int j = 0; j < topology_weights[i].size(); j++) {
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topology_weights[i][j] = INFINITE_LATENCY;
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// initialize to invalid values
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m_component_latencies[i][j] = -1;
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// initially assume direct connections / no intermediate
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// switches between components
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m_component_inter_switches[i][j] = 0;
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}
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}
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// Set identity weights to zero
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for (int i = 0; i < topology_weights.size(); i++) {
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topology_weights[i][i] = 0;
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}
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// Fill in the topology weights and bandwidth multipliers
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for (LinkMap::const_iterator i = m_link_map.begin();
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i != m_link_map.end(); ++i) {
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std::pair<int, int> src_dest = (*i).first;
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BasicLink* link = (*i).second.link;
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int src = src_dest.first;
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int dst = src_dest.second;
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m_component_latencies[src][dst] = link->m_latency;
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topology_weights[src][dst] = link->m_weight;
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}
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// Walk topology and hookup the links
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Matrix dist = shortest_path(topology_weights, m_component_latencies,
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m_component_inter_switches);
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for (int i = 0; i < topology_weights.size(); i++) {
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for (int j = 0; j < topology_weights[i].size(); j++) {
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int weight = topology_weights[i][j];
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if (weight > 0 && weight != INFINITE_LATENCY) {
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NetDest destination_set = shortest_path_to_node(i, j,
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topology_weights, dist);
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makeLink(net, i, j, destination_set, isReconfiguration);
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}
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}
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}
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}
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void
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Topology::addLink(SwitchID src, SwitchID dest, BasicLink* link,
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LinkDirection dir)
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{
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assert(src <= m_number_of_switches+m_nodes+m_nodes);
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assert(dest <= m_number_of_switches+m_nodes+m_nodes);
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std::pair<int, int> src_dest_pair;
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LinkEntry link_entry;
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src_dest_pair.first = src;
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src_dest_pair.second = dest;
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link_entry.direction = dir;
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link_entry.link = link;
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m_link_map[src_dest_pair] = link_entry;
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}
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void
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Topology::makeLink(Network *net, SwitchID src, SwitchID dest,
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const NetDest& routing_table_entry, bool isReconfiguration)
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{
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// Make sure we're not trying to connect two end-point nodes
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// directly together
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assert(src >= 2 * m_nodes || dest >= 2 * m_nodes);
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std::pair<int, int> src_dest;
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LinkEntry link_entry;
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if (src < m_nodes) {
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src_dest.first = src;
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src_dest.second = dest;
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link_entry = m_link_map[src_dest];
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net->makeInLink(src, dest - (2 * m_nodes), link_entry.link,
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link_entry.direction,
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routing_table_entry,
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isReconfiguration);
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} else if (dest < 2*m_nodes) {
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assert(dest >= m_nodes);
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NodeID node = dest - m_nodes;
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src_dest.first = src;
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src_dest.second = dest;
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link_entry = m_link_map[src_dest];
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net->makeOutLink(src - (2 * m_nodes), node, link_entry.link,
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link_entry.direction,
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routing_table_entry,
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isReconfiguration);
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} else {
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assert((src >= 2 * m_nodes) && (dest >= 2 * m_nodes));
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src_dest.first = src;
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src_dest.second = dest;
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link_entry = m_link_map[src_dest];
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net->makeInternalLink(src - (2 * m_nodes), dest - (2 * m_nodes),
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link_entry.link, link_entry.direction,
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routing_table_entry, isReconfiguration);
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}
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}
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void
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Topology::printStats(std::ostream& out) const
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{
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for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) {
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m_controller_vector[cntrl]->printStats(out);
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}
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}
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void
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Topology::clearStats()
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{
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for (int cntrl = 0; cntrl < m_controller_vector.size(); cntrl++) {
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m_controller_vector[cntrl]->clearStats();
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}
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}
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void
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Topology::printConfig(std::ostream& out) const
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{
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if (m_print_config == false)
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return;
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assert(m_component_latencies.size() > 0);
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out << "--- Begin Topology Print ---" << endl
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<< endl
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<< "Topology print ONLY indicates the _NETWORK_ latency between two "
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<< "machines" << endl
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<< "It does NOT include the latency within the machines" << endl
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<< endl;
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for (int m = 0; m < MachineType_NUM; m++) {
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int i_end = MachineType_base_count((MachineType)m);
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for (int i = 0; i < i_end; i++) {
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MachineID cur_mach = {(MachineType)m, i};
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out << cur_mach << " Network Latencies" << endl;
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for (int n = 0; n < MachineType_NUM; n++) {
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int j_end = MachineType_base_count((MachineType)n);
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for (int j = 0; j < j_end; j++) {
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MachineID dest_mach = {(MachineType)n, j};
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if (cur_mach == dest_mach)
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continue;
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int src = MachineType_base_number((MachineType)m) + i;
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int dst = MachineType_base_number(MachineType_NUM) +
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MachineType_base_number((MachineType)n) + j;
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int link_latency = m_component_latencies[src][dst];
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int intermediate_switches =
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m_component_inter_switches[src][dst];
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// NOTE switches are assumed to have single
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// cycle latency
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out << " " << cur_mach << " -> " << dest_mach
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<< " net_lat: "
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<< link_latency + intermediate_switches << endl;
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}
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}
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out << endl;
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}
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}
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out << "--- End Topology Print ---" << endl;
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}
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// The following all-pairs shortest path algorithm is based on the
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// discussion from Cormen et al., Chapter 26.1.
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void
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extend_shortest_path(Matrix& current_dist, Matrix& latencies,
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Matrix& inter_switches)
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{
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bool change = true;
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int nodes = current_dist.size();
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while (change) {
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change = false;
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for (int i = 0; i < nodes; i++) {
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for (int j = 0; j < nodes; j++) {
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int minimum = current_dist[i][j];
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int previous_minimum = minimum;
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int intermediate_switch = -1;
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for (int k = 0; k < nodes; k++) {
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minimum = min(minimum,
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current_dist[i][k] + current_dist[k][j]);
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if (previous_minimum != minimum) {
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intermediate_switch = k;
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inter_switches[i][j] =
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inter_switches[i][k] +
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inter_switches[k][j] + 1;
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}
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previous_minimum = minimum;
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}
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if (current_dist[i][j] != minimum) {
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change = true;
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current_dist[i][j] = minimum;
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assert(intermediate_switch >= 0);
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assert(intermediate_switch < latencies[i].size());
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latencies[i][j] = latencies[i][intermediate_switch] +
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latencies[intermediate_switch][j];
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}
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}
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}
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}
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}
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Matrix
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shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches)
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{
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Matrix dist = weights;
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extend_shortest_path(dist, latencies, inter_switches);
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return dist;
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}
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bool
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link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final,
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const Matrix& weights, const Matrix& dist)
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{
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return weights[src][next] + dist[next][final] == dist[src][final];
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}
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NetDest
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shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights,
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const Matrix& dist)
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{
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NetDest result;
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int d = 0;
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int machines;
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int max_machines;
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machines = MachineType_NUM;
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max_machines = MachineType_base_number(MachineType_NUM);
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for (int m = 0; m < machines; m++) {
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for (int i = 0; i < MachineType_base_count((MachineType)m); i++) {
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// we use "d+max_machines" below since the "destination"
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// switches for the machines are numbered
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// [MachineType_base_number(MachineType_NUM)...
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// 2*MachineType_base_number(MachineType_NUM)-1] for the
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// component network
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if (link_is_shortest_path_to_node(src, next, d + max_machines,
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weights, dist)) {
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MachineID mach = {(MachineType)m, i};
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result.add(mach);
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}
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d++;
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}
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}
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DPRINTF(RubyNetwork, "Returning shortest path\n"
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"(src-(2*max_machines)): %d, (next-(2*max_machines)): %d, "
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"src: %d, next: %d, result: %s\n",
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(src-(2*max_machines)), (next-(2*max_machines)),
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src, next, result);
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return result;
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}
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Topology *
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TopologyParams::create()
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{
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return new Topology(this);
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}
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