54cc0053f0
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
119 lines
3.5 KiB
C++
119 lines
3.5 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Lisa Hsu
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* Nathan Binkert
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* Steve Raasch
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*/
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#include <iomanip>
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#include "base/loader/symtab.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "enums/OpClass.hh"
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using namespace std;
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using namespace TheISA;
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namespace Trace {
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void
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Trace::ExeTracerRecord::dump()
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{
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ostream &outs = Trace::output();
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if (IsOn(ExecTicks))
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ccprintf(outs, "%7d: ", when);
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outs << thread->getCpuPtr()->name() << " ";
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if (IsOn(ExecSpeculative))
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outs << (misspeculating ? "-" : "+") << " ";
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if (IsOn(ExecThread))
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outs << "T" << thread->getThreadNum() << " : ";
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std::string sym_str;
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Addr sym_addr;
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if (debugSymbolTable
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&& IsOn(ExecSymbol)
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&& debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
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if (PC != sym_addr)
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sym_str += csprintf("+%d", PC - sym_addr);
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outs << "@" << sym_str << " : ";
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}
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else {
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outs << "0x" << hex << PC << " : ";
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}
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//
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// Print decoded instruction
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//
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outs << setw(26) << left;
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outs << staticInst->disassemble(PC, debugSymbolTable);
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outs << " : ";
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if (IsOn(ExecOpClass)) {
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outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
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}
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if (IsOn(ExecResult) && data_status != DataInvalid) {
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ccprintf(outs, " D=%#018x", data.as_int);
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}
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if (IsOn(ExecEffAddr) && addr_valid)
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outs << " A=0x" << hex << addr;
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if (IsOn(ExecFetchSeq) && fetch_seq_valid)
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outs << " FetchSeq=" << dec << fetch_seq;
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if (IsOn(ExecCPSeq) && cp_seq_valid)
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outs << " CPSeq=" << dec << cp_seq;
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//
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// End of line...
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//
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outs << endl;
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}
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/* namespace Trace */ }
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////////////////////////////////////////////////////////////////////////
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//
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// ExeTracer Simulation Object
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//
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Trace::ExeTracer *
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ExeTracerParams::create()
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{
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return new Trace::ExeTracer(this);
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};
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