Ali Saidi ecbb8debf6 Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts ... getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28		2006-12-06 14:29:10 -05:00
..
boot	netperf-maerts-client.rcS:	2006-11-30 11:53:33 -05:00
common	Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts	2006-12-06 14:29:10 -05:00
example	automatically build sparc system or alpha system.	2006-12-04 19:37:50 -05:00
splash2	Update splash2 config files	2006-11-13 16:09:47 -05:00