gem5/util/tlm/tlm.py
Matthias Jung 8723b08dbf misc: Coupling gem5 with SystemC TLM2.0
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.

Compared to the original patch a TLM memory manager was added. Furthermore, the
transaction object was removed and for each TLM payload a PacketPointer that
points to the original gem5 packet is added as an TLM extension.  For event
handling single events are now created.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-08-03 23:08:40 -05:00

78 lines
3.1 KiB
Python

# Copyright (c) 2015, University of Kaiserslautern
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#
# Authors: Matthias Jung
import m5
from m5.objects import *
# This configuration shows a simple setup of a TrafficGen (CPU) and an
# external TLM port for SystemC co-simulation
#
# Base System Architecture:
# +-------------+ +-----+ ^
# | System Port | | CPU | |
# +-------+-----+ +--+--+ |
# | | | gem5 World
# | +----+ | (see this file)
# | | |
# +-------v------v-------+ |
# | Membus | v
# +----------------+-----+ External Port (see sc_port.*)
# | ^
# +---v---+ | TLM World
# | TLM | | (see sc_target.*)
# +-------+ v
#
# Create a system with a Crossbar and a TrafficGenerator as CPU:
system = System()
system.membus = IOXBar(width = 16)
system.physmem = SimpleMemory() # This must be instanciated, even if not needed
system.cpu = TrafficGen(config_file = "tgen.cfg")
system.clk_domain = SrcClockDomain(clock = '1.5GHz',
voltage_domain = VoltageDomain(voltage = '1V'))
# Create a external TLM port:
system.tlm = ExternalSlave()
system.tlm.addr_ranges = [AddrRange('512MB')]
system.tlm.port_type = "tlm"
system.tlm.port_data = "memory"
# Route the connections:
system.cpu.port = system.membus.slave
system.system_port = system.membus.slave
system.membus.master = system.tlm.port
# Start the simulation:
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
m5.instantiate()
m5.simulate() #Simulation time specified later on commandline