483 lines
12 KiB
C
483 lines
12 KiB
C
/*
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* Copyright (c) 1993-1994 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef FROMHUDSONOSF_INCLUDED
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#define FROMHUDSONOSF_INCLUDED 1
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#define __OSF_LOADED 1
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/*
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** Seg0 and Seg1 Virtual Address (VA) Format
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**
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** Loc Size Name Function
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** ----- ---- ---- ---------------------------------
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** <42:33> 10 SEG1 First level page table offset
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** <32:23> 10 SEG2 Second level page table offset
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** <22:13> 10 SEG3 Third level page table offset
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** <12:00> 13 OFFSET Byte within page offset
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*/
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#define VA_V_SEG1 33
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#define VA_M_SEG1 (0x3FF<<VA_V_SEG1)
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#define VA_V_SEG2 23
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#define VA_M_SEG2 (0x3FF<<VA_V_SEG2)
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#define VA_V_SEG3 13
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#define VA_M_SEG3 (0x3FF<<VA_V_SEG3)
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#define VA_V_OFFSET 0
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#define VA_M_OFFSET 0x1FFF
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/*
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** Virtual Address Options: 8K byte page size
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*/
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#define VA_S_SIZE 43
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#define VA_S_OFF 13
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#define va_s_off 13
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#define VA_S_SEG 10
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#define VA_S_PAGE_SIZE 8192
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/*
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** Page Table Entry (PTE) Format
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**
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** Extent Size Name Function
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** ------ ---- ---- ---------------------------------
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** <63:32> 32 PFN Page Frame Number
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** <31:16> 16 SW Reserved for software
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** <15:14> 2 RSV0 Reserved for hardware SBZ
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** <13> 1 UWE User Write Enable
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** <12> 1 KWE Kernel Write Enable
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** <11:10> 2 RSV1 Reserved for hardware SBZ
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** <9> 1 URE User Read Enable
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** <8> 1 KRE Kernel Read Enable
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** <7> 1 RSV2 Reserved for hardware SBZ
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** <6:5> 2 GH Granularity Hint
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** <4> 1 ASM Address Space Match
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** <3> 1 FOE Fault On Execute
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** <2> 1 FOW Fault On Write
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** <1> 1 FOR Fault On Read
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** <0> 1 V Valid
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*/
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#define PTE_V_PFN 32
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#define PTE_M_PFN 0xFFFFFFFF00000000
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#define PTE_V_SW 16
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#define PTE_M_SW 0x00000000FFFF0000
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#define PTE_V_UWE 13
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#define PTE_M_UWE (1<<PTE_V_UWE)
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#define PTE_V_KWE 12
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#define PTE_M_KWE (1<<PTE_V_KWE)
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#define PTE_V_URE 9
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#define PTE_M_URE (1<<PTE_V_URE)
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#define PTE_V_KRE 8
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#define PTE_M_KRE (1<<PTE_V_KRE)
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#define PTE_V_GH 5
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#define PTE_M_GH (3<<PTE_V_GH)
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#define PTE_V_ASM 4
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#define PTE_M_ASM (1<<PTE_V_ASM)
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#define PTE_V_FOE 3
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#define PTE_M_FOE (1<<PTE_V_FOE)
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#define PTE_V_FOW 2
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#define PTE_M_FOW (1<<PTE_V_FOW)
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#define PTE_V_FOR 1
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#define PTE_M_FOR (1<<PTE_V_FOR)
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#define PTE_V_VALID 0
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#define PTE_M_VALID (1<<PTE_V_VALID)
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#define PTE_M_KSEG 0x1111
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#define PTE_M_PROT 0x3300
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#define pte_m_prot 0x3300
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/*
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** System Entry Instruction Fault (entIF) Constants:
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*/
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#define IF_K_BPT 0x0
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#define IF_K_BUGCHK 0x1
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#define IF_K_GENTRAP 0x2
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#define IF_K_FEN 0x3
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#define IF_K_OPCDEC 0x4
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/*
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** System Entry Hardware Interrupt (entInt) Constants:
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*/
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#define INT_K_IP 0x0
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#define INT_K_CLK 0x1
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#define INT_K_MCHK 0x2
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#define INT_K_DEV 0x3
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#define INT_K_PERF 0x4
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/*
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** System Entry MM Fault (entMM) Constants:
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*/
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#define MM_K_TNV 0x0
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#define MM_K_ACV 0x1
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#define MM_K_FOR 0x2
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#define MM_K_FOE 0x3
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#define MM_K_FOW 0x4
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/*
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** Process Control Block (PCB) Offsets:
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*/
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#define PCB_Q_KSP 0x0000
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#define PCB_Q_USP 0x0008
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#define PCB_Q_PTBR 0x0010
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#define PCB_L_PCC 0x0018
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#define PCB_L_ASN 0x001C
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#define PCB_Q_UNIQUE 0x0020
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#define PCB_Q_FEN 0x0028
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#define PCB_Q_RSV0 0x0030
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#define PCB_Q_RSV1 0x0038
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/*
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** Processor Status Register (PS) Bit Summary
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**
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** Extent Size Name Function
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** ------ ---- ---- ---------------------------------
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** <3> 1 CM Current Mode
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** <2:0> 3 IPL Interrupt Priority Level
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**/
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#define PS_V_CM 3
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#define PS_M_CM (1<<PS_V_CM)
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#define PS_V_IPL 0
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#define PS_M_IPL (7<<PS_V_IPL)
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#define PS_K_KERN (0<<PS_V_CM)
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#define PS_K_USER (1<<PS_V_CM)
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#define IPL_K_ZERO 0x0
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#define IPL_K_SW0 0x1
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#define IPL_K_SW1 0x2
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#define IPL_K_DEV0 0x3
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#define IPL_K_DEV1 0x4
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#define IPL_K_CLK 0x5
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#define IPL_K_RT 0x6
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#define IPL_K_PERF 0x6
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#define IPL_K_PFAIL 0x6
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#define IPL_K_MCHK 0x7
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#define IPL_K_LOW 0x0
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#define IPL_K_HIGH 0x7
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/*
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** SCB Offset Definitions:
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*/
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#define SCB_Q_FEN 0x0010
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#define SCB_Q_ACV 0x0080
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#define SCB_Q_TNV 0x0090
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#define SCB_Q_FOR 0x00A0
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#define SCB_Q_FOW 0x00B0
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#define SCB_Q_FOE 0x00C0
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#define SCB_Q_ARITH 0x0200
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#define SCB_Q_KAST 0x0240
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#define SCB_Q_EAST 0x0250
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#define SCB_Q_SAST 0x0260
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#define SCB_Q_UAST 0x0270
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#define SCB_Q_UNALIGN 0x0280
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#define SCB_Q_BPT 0x0400
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#define SCB_Q_BUGCHK 0x0410
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#define SCB_Q_OPCDEC 0x0420
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#define SCB_Q_ILLPAL 0x0430
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#define SCB_Q_TRAP 0x0440
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#define SCB_Q_CHMK 0x0480
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#define SCB_Q_CHME 0x0490
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#define SCB_Q_CHMS 0x04A0
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#define SCB_Q_CHMU 0x04B0
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#define SCB_Q_SW0 0x0500
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#define SCB_Q_SW1 0x0510
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#define SCB_Q_SW2 0x0520
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#define SCB_Q_SW3 0x0530
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#define SCB_Q_SW4 0x0540
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#define SCB_Q_SW5 0x0550
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#define SCB_Q_SW6 0x0560
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#define SCB_Q_SW7 0x0570
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#define SCB_Q_SW8 0x0580
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#define SCB_Q_SW9 0x0590
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#define SCB_Q_SW10 0x05A0
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#define SCB_Q_SW11 0x05B0
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#define SCB_Q_SW12 0x05C0
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#define SCB_Q_SW13 0x05D0
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#define SCB_Q_SW14 0x05E0
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#define SCB_Q_SW15 0x05F0
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#define SCB_Q_CLOCK 0x0600
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#define SCB_Q_INTER 0x0610
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#define SCB_Q_SYSERR 0x0620
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#define SCB_Q_PROCERR 0x0630
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#define SCB_Q_PWRFAIL 0x0640
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#define SCB_Q_PERFMON 0x0650
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#define SCB_Q_SYSMCHK 0x0660
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#define SCB_Q_PROCMCHK 0x0670
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#define SCB_Q_PASSREL 0x0680
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/*
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** Stack Frame (FRM) Offsets:
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**
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** There are two types of system entries for OSF/1 - those for the
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** callsys CALL_PAL function and those for exceptions and interrupts.
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** Both entry types use the same stack frame layout. The stack frame
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** contains space for the PC, the PS, the saved GP, and the saved
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** argument registers a0, a1, and a2. On entry, SP points to the
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** saved PS.
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*/
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#define FRM_Q_PS 0x0000
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#define FRM_Q_PC 0x0008
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#define FRM_Q_GP 0x0010
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#define FRM_Q_A0 0x0018
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#define FRM_Q_A1 0x0020
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#define FRM_Q_A2 0x0028
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#define FRM_K_SIZE 48
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#define STACK_FRAME(tmp1,tmp2) \
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sll ps, 63-PS_V_CM, p7; \
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bge p7, 0f; \
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bis zero, zero, ps; \
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mtpr sp, ptUsp; \
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mfpr sp, ptKsp; \
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0: lda sp, 0-FRM_K_SIZE(sp); \
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stq tmp1, FRM_Q_PS(sp); \
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stq tmp2, FRM_Q_PC(sp); \
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stq gp, FRM_Q_GP(sp); \
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stq a0, FRM_Q_A0(sp); \
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stq a1, FRM_Q_A1(sp); \
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stq a2, FRM_Q_A2(sp)
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/*
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** Halt Codes:
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*/
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#define HLT_K_RESET 0x0000
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#define HLT_K_HW_HALT 0x0001
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#define HLT_K_KSP_INVAL 0x0002
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#define HLT_K_SCBB_INVAL 0x0003
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#define HLT_K_PTBR_INVAL 0x0004
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#define HLT_K_SW_HALT 0x0005
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#define HLT_K_DBL_MCHK 0x0006
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#define HLT_K_MCHK_FROM_PAL 0x0007
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/*
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** Machine Check Codes:
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*/
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#define MCHK_K_TPERR 0x0080
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#define MCHK_K_TCPERR 0x0082
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#define MCHK_K_HERR 0x0084
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#define MCHK_K_ECC_C 0x0086
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#define MCHK_K_ECC_NC 0x0088
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#define MCHK_K_UNKNOWN 0x008A
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#define MCHK_K_CACKSOFT 0x008C
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#define MCHK_K_BUGCHECK 0x008E
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#define MCHK_K_OS_BUGCHECK 0x0090
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#define MCHK_K_DCPERR 0x0092
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#define MCHK_K_ICPERR 0x0094
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#define MCHK_K_RETRY_IRD 0x0096
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#define MCHK_K_PROC_HERR 0x0098
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/*
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** System Machine Check Codes:
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*/
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#define MCHK_K_READ_NXM 0x0200
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#define MCHK_K_SYS_HERR 0x0202
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/*
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** Machine Check Error Status Summary (MCES) Register Format
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**
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** Extent Size Name Function
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** ------ ---- ---- ---------------------------------
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** <0> 1 MIP Machine check in progress
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** <1> 1 SCE System correctable error in progress
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** <2> 1 PCE Processor correctable error in progress
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** <3> 1 DPC Disable PCE error reporting
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** <4> 1 DSC Disable SCE error reporting
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*/
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#define MCES_V_MIP 0
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#define MCES_M_MIP (1<<MCES_V_MIP)
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#define MCES_V_SCE 1
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#define MCES_M_SCE (1<<MCES_V_SCE)
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#define MCES_V_PCE 2
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#define MCES_M_PCE (1<<MCES_V_PCE)
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#define MCES_V_DPC 3
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#define MCES_M_DPC (1<<MCES_V_DPC)
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#define MCES_V_DSC 4
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#define MCES_M_DSC (1<<MCES_V_DSC)
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#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
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| MCES_M_DSC)
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/*
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** Who-Am-I (WHAMI) Register Format
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**
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** Extent Size Name Function
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** ------ ---- ---- ---------------------------------
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** <7:0> 8 ID Who-Am-I identifier
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** <15:8> 1 SWAP Swap PALcode flag - character 'S'
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*/
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#define WHAMI_V_SWAP 8
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#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP)
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#define WHAMI_V_ID 0
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#define WHAMI_M_ID 0xFF
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#define WHAMI_K_SWAP 0x53 /* Character 'S' */
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/*
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** Conventional Register Usage Definitions
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**
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** Assembler temporary `at' is `AT' so it doesn't conflict with the
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** `.set at' assembler directive.
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*/
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#define v0 $0 /* Function Return Value Register */
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#define t0 $1 /* Scratch (Temporary) Registers ... */
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#define t1 $2
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#define t2 $3
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#define t3 $4
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#define t4 $5
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#define t5 $6
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#define t6 $7
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#define t7 $8
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#define s0 $9 /* Saved (Non-Volatile) Registers ... */
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#define s1 $10
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#define s2 $11
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#define s3 $12
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#define s4 $13
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#define s5 $14
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#define fp $15 /* Frame Pointer Register, Or S6 */
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#define s6 $15
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#define a0 $16 /* Argument Registers ... */
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#define a1 $17
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#define a2 $18
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#define a3 $19
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#define a4 $20
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#define a5 $21
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#define t8 $22 /* Scratch (Temporary) Registers ... */
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#define t9 $23
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#define t10 $24
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#define t11 $25
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#define ra $26 /* Return Address Register */
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#define pv $27 /* Procedure Value Register, Or T12 */
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#define t12 $27
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#define AT $28 /* Assembler Temporary (Volatile) Register */
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#define gp $29 /* Global Pointer Register */
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#define sp $30 /* Stack Pointer Register */
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#define zero $31 /* Zero Register */
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/*
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** OSF/1 Unprivileged CALL_PAL Entry Offsets:
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**
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** Entry Name Offset (Hex)
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**
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** bpt 0080
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** bugchk 0081
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** callsys 0083
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** imb 0086
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** rdunique 009E
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** wrunique 009F
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** gentrap 00AA
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** dbgstop 00AD
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*/
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#define UNPRIV 0x80
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#define PAL_BPT_ENTRY 0x80
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#define PAL_BUGCHK_ENTRY 0x81
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#define PAL_CALLSYS_ENTRY 0x83
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#define PAL_IMB_ENTRY 0x86
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#define PAL_RDUNIQUE_ENTRY 0x9E
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#define PAL_WRUNIQUE_ENTRY 0x9F
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#define PAL_GENTRAP_ENTRY 0xAA
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#if defined(KDEBUG)
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#define PAL_DBGSTOP_ENTRY 0xAD
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/* #define NUM_UNPRIV_CALL_PALS 10 */
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#else
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/* #define NUM_UNPRIV_CALL_PALS 9 */
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#endif /* KDEBUG */
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/*
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** OSF/1 Privileged CALL_PAL Entry Offsets:
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**
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** Entry Name Offset (Hex)
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**
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** halt 0000
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** cflush 0001
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** draina 0002
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** cserve 0009
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** swppal 000A
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** rdmces 0010
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** wrmces 0011
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** wrfen 002B
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** wrvptptr 002D
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** swpctx 0030
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** wrval 0031
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** rdval 0032
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** tbi 0033
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** wrent 0034
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** swpipl 0035
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** rdps 0036
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** wrkgp 0037
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** wrusp 0038
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** rdusp 003A
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** whami 003C
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** retsys 003D
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** rti 003F
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*/
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#define PAL_HALT_ENTRY 0x0000
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#define PAL_CFLUSH_ENTRY 0x0001
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#define PAL_DRAINA_ENTRY 0x0002
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#define PAL_CSERVE_ENTRY 0x0009
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#define PAL_SWPPAL_ENTRY 0x000A
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#define PAL_WRIPIR_ENTRY 0x000D
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#define PAL_RDMCES_ENTRY 0x0010
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#define PAL_WRMCES_ENTRY 0x0011
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#define PAL_WRFEN_ENTRY 0x002B
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#define PAL_WRVPTPTR_ENTRY 0x002D
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#define PAL_SWPCTX_ENTRY 0x0030
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#define PAL_WRVAL_ENTRY 0x0031
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#define PAL_RDVAL_ENTRY 0x0032
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#define PAL_TBI_ENTRY 0x0033
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#define PAL_WRENT_ENTRY 0x0034
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#define PAL_SWPIPL_ENTRY 0x0035
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#define PAL_RDPS_ENTRY 0x0036
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#define PAL_WRKGP_ENTRY 0x0037
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#define PAL_WRUSP_ENTRY 0x0038
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#define PAL_RDUSP_ENTRY 0x003A
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#define PAL_WHAMI_ENTRY 0x003C
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#define PAL_RETSYS_ENTRY 0x003D
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#define PAL_RTI_ENTRY 0x003F
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#define NUM_PRIV_CALL_PALS 23
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#endif
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