7dd171ba96
This patch updates the 'learning gem5' example scripts to match the recent push of the SMT patches.
107 lines
4.2 KiB
Python
107 lines
4.2 KiB
Python
# -*- coding: utf-8 -*-
|
|
# Copyright (c) 2015 Jason Power
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions are
|
|
# met: redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer;
|
|
# redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution;
|
|
# neither the name of the copyright holders nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
#
|
|
# Authors: Jason Power
|
|
|
|
""" This file creates a barebones system and executes 'hello', a simple Hello
|
|
World application.
|
|
See Part 1, Chapter 2: Creating a simple configuration script in the
|
|
learning_gem5 book for more information about this script.
|
|
|
|
IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
|
|
also needs to be updated. For now, email Jason <power.jg@gmail.com>
|
|
|
|
"""
|
|
|
|
# import the m5 (gem5) library created when gem5 is built
|
|
import m5
|
|
# import all of the SimObjects
|
|
from m5.objects import *
|
|
|
|
# create the system we are going to simulate
|
|
system = System()
|
|
|
|
# Set the clock fequency of the system (and all of its children)
|
|
system.clk_domain = SrcClockDomain()
|
|
system.clk_domain.clock = '1GHz'
|
|
system.clk_domain.voltage_domain = VoltageDomain()
|
|
|
|
# Set up the system
|
|
system.mem_mode = 'timing' # Use timing accesses
|
|
system.mem_ranges = [AddrRange('512MB')] # Create an address range
|
|
|
|
# Create a simple CPU
|
|
system.cpu = TimingSimpleCPU()
|
|
|
|
# Create a memory bus, a system crossbar, in this case
|
|
system.membus = SystemXBar()
|
|
|
|
# Hook the CPU ports up to the membus
|
|
system.cpu.icache_port = system.membus.slave
|
|
system.cpu.dcache_port = system.membus.slave
|
|
|
|
# create the interrupt controller for the CPU and connect to the membus
|
|
system.cpu.createInterruptController()
|
|
|
|
# For x86 only, make sure the interrupts are connected to the memory
|
|
# Note: these are directly connected to the memory bus and are not cached
|
|
if m5.defines.buildEnv['TARGET_ISA'] == "x86":
|
|
system.cpu.interrupts[0].pio = system.membus.master
|
|
system.cpu.interrupts[0].int_master = system.membus.slave
|
|
system.cpu.interrupts[0].int_slave = system.membus.master
|
|
|
|
# Create a DDR3 memory controller and connect it to the membus
|
|
system.mem_ctrl = DDR3_1600_x64()
|
|
system.mem_ctrl.range = system.mem_ranges[0]
|
|
system.mem_ctrl.port = system.membus.master
|
|
|
|
# Connect the system up to the membus
|
|
system.system_port = system.membus.slave
|
|
|
|
# get ISA for the binary to run.
|
|
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
|
|
|
|
# Run 'hello' and use the compiled ISA to find the binary
|
|
binary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
|
|
|
|
# Create a process for a simple "Hello World" application
|
|
process = LiveProcess()
|
|
# Set the command
|
|
# cmd is a list which begins with the executable (like argv)
|
|
process.cmd = [binary]
|
|
# Set the cpu to use the process as its workload and create thread contexts
|
|
system.cpu.workload = process
|
|
system.cpu.createThreads()
|
|
|
|
# set up the root SimObject and start the simulation
|
|
root = Root(full_system = False, system = system)
|
|
# instantiate all of the objects we've created above
|
|
m5.instantiate()
|
|
|
|
print "Beginning simulation!"
|
|
exit_event = m5.simulate()
|
|
print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
|