into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 08ae5e999d9b313e3e40cb6d58863905b70ca781
1219 lines
32 KiB
C++
1219 lines
32 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cmath>
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#include <cstdio>
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#include <cstdlib>
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#include <iostream>
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#include <iomanip>
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#include <list>
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#include <sstream>
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#include <string>
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#include "arch/utility.hh"
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/pollevent.hh"
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#include "base/range.hh"
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#include "base/stats/events.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/profile.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/simple/cpu.hh"
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#include "cpu/smt.hh"
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#include "cpu/static_inst.hh"
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#include "kern/kernel_stats.hh"
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#include "sim/byteswap.hh"
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#include "sim/builder.hh"
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#include "sim/debug.hh"
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#include "sim/host.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_object.hh"
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#include "sim/stats.hh"
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#if FULL_SYSTEM
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#include "base/remote_gdb.hh"
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//#include "mem/functional/memory_control.hh"
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//#include "mem/functional/physical.hh"
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#include "sim/system.hh"
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#include "arch/tlb.hh"
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#include "arch/stacktrace.hh"
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#include "arch/vtophys.hh"
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#else // !FULL_SYSTEM
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#include "mem/mem_object.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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using namespace TheISA;
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SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
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: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
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{
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}
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void
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SimpleCPU::init()
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{
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//Create Memory Ports (conect them up)
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Port *mem_dport = mem->getPort("");
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dcachePort.setPeer(mem_dport);
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mem_dport->setPeer(&dcachePort);
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Port *mem_iport = mem->getPort("");
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icachePort.setPeer(mem_iport);
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mem_iport->setPeer(&icachePort);
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BaseCPU::init();
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#if FULL_SYSTEM
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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// initialize CPU, including PC
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TheISA::initCPU(xc, xc->readCpuId());
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}
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#endif
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}
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void
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SimpleCPU::TickEvent::process()
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{
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int count = width;
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do {
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cpu->tick();
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} while (--count > 0 && cpu->status() == Running);
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}
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const char *
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SimpleCPU::TickEvent::description()
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{
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return "SimpleCPU tick event";
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}
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bool
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SimpleCPU::CpuPort::recvTiming(Packet &pkt)
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{
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cpu->processResponse(pkt);
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return true;
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}
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Tick
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SimpleCPU::CpuPort::recvAtomic(Packet &pkt)
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{
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panic("CPU doesn't expect callback!");
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return curTick;
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}
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void
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SimpleCPU::CpuPort::recvFunctional(Packet &pkt)
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{
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panic("CPU doesn't expect callback!");
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}
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void
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SimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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cpu->recvStatusChange(status);
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}
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Packet *
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SimpleCPU::CpuPort::recvRetry()
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{
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return cpu->processRetry();
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}
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SimpleCPU::SimpleCPU(Params *p)
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#if !FULL_SYSTEM
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: BaseCPU(p), mem(p->mem), icachePort(this),
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dcachePort(this), tickEvent(this, p->width), cpuXC(NULL)
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#else
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: BaseCPU(p), icachePort(this), dcachePort(this),
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tickEvent(this, p->width), cpuXC(NULL)
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#endif
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{
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_status = Idle;
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#if FULL_SYSTEM
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cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
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#else
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cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
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/* asid */ 0, mem);
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#endif // !FULL_SYSTEM
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xcProxy = cpuXC->getProxy();
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#if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
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ifetch_req = new CpuRequest;
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ifetch_req->asid = 0;
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ifetch_req->size = sizeof(MachInst);
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ifetch_pkt = new Packet;
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ifetch_pkt->cmd = Read;
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ifetch_pkt->data = (uint8_t *)&inst;
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ifetch_pkt->req = ifetch_req;
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ifetch_pkt->size = sizeof(MachInst);
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data_read_req = new CpuRequest;
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data_read_req->asid = 0;
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data_read_pkt = new Packet;
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data_read_pkt->cmd = Read;
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data_read_pkt->data = new uint8_t[8];
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data_read_pkt->req = data_read_req;
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data_write_req = new CpuRequest;
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data_write_req->asid = 0;
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data_write_pkt = new Packet;
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data_write_pkt->cmd = Write;
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data_write_pkt->req = data_write_req;
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#endif
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numInst = 0;
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startNumInst = 0;
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numLoad = 0;
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startNumLoad = 0;
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lastIcacheStall = 0;
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lastDcacheStall = 0;
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execContexts.push_back(xcProxy);
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}
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SimpleCPU::~SimpleCPU()
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{
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}
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void
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SimpleCPU::switchOut(Sampler *s)
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{
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sampler = s;
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if (status() == DcacheWaitResponse) {
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DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n");
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_status = DcacheWaitSwitch;
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}
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else {
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_status = SwitchedOut;
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if (tickEvent.scheduled())
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tickEvent.squash();
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sampler->signalSwitched();
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}
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}
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void
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SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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BaseCPU::takeOverFrom(oldCPU);
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assert(!tickEvent.scheduled());
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// if any of this CPU's ExecContexts are active, mark the CPU as
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// running and schedule its tick event.
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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if (xc->status() == ExecContext::Active && _status != Running) {
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_status = Running;
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tickEvent.schedule(curTick);
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}
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}
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}
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void
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SimpleCPU::activateContext(int thread_num, int delay)
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{
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assert(thread_num == 0);
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assert(cpuXC);
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assert(_status == Idle);
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notIdleFraction++;
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scheduleTickEvent(delay);
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_status = Running;
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}
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void
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SimpleCPU::suspendContext(int thread_num)
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{
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assert(thread_num == 0);
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assert(cpuXC);
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assert(_status == Running);
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notIdleFraction--;
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unscheduleTickEvent();
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_status = Idle;
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}
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void
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SimpleCPU::deallocateContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::haltContext(int thread_num)
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{
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// for now, these are equivalent
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suspendContext(thread_num);
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}
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void
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SimpleCPU::regStats()
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{
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using namespace Stats;
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BaseCPU::regStats();
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numInsts
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.name(name() + ".num_insts")
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.desc("Number of instructions executed")
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;
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numMemRefs
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.name(name() + ".num_refs")
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.desc("Number of memory references")
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;
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notIdleFraction
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.name(name() + ".not_idle_fraction")
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.desc("Percentage of non-idle cycles")
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;
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idleFraction
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.name(name() + ".idle_fraction")
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.desc("Percentage of idle cycles")
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;
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icacheStallCycles
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.name(name() + ".icache_stall_cycles")
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.desc("ICache total stall cycles")
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.prereq(icacheStallCycles)
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;
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dcacheStallCycles
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.name(name() + ".dcache_stall_cycles")
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.desc("DCache total stall cycles")
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.prereq(dcacheStallCycles)
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;
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icacheRetryCycles
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.name(name() + ".icache_retry_cycles")
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.desc("ICache total retry cycles")
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.prereq(icacheRetryCycles)
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;
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dcacheRetryCycles
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.name(name() + ".dcache_retry_cycles")
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.desc("DCache total retry cycles")
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.prereq(dcacheRetryCycles)
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;
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idleFraction = constant(1.0) - notIdleFraction;
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}
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void
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SimpleCPU::resetStats()
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{
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startNumInst = numInst;
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notIdleFraction = (_status != Idle);
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}
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void
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SimpleCPU::serialize(ostream &os)
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{
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BaseCPU::serialize(os);
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SERIALIZE_ENUM(_status);
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SERIALIZE_SCALAR(inst);
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nameOut(os, csprintf("%s.xc", name()));
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cpuXC->serialize(os);
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
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}
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void
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SimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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BaseCPU::unserialize(cp, section);
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UNSERIALIZE_ENUM(_status);
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UNSERIALIZE_SCALAR(inst);
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cpuXC->unserialize(cp, csprintf("%s.xc", section));
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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}
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void
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change_thread_state(int thread_number, int activate, int priority)
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{
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}
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Fault
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SimpleCPU::copySrcTranslate(Addr src)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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int offset = src & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(src & PageMask) != ((src + blk_size) & PageMask) &&
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(src >> 40) != 0xfffffc) {
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warn("Copied block source spans pages %x.", src);
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no_warn = false;
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}
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memReq->reset(src & ~(blk_size - 1), blk_size);
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// translate to physical address Fault fault = cpuXC->translateDataReadReq(req);
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if (fault == NoFault) {
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cpuXC->copySrcAddr = src;
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cpuXC->copySrcPhysAddr = memReq->paddr + offset;
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} else {
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assert(!fault->isAlignmentFault());
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cpuXC->copySrcAddr = 0;
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cpuXC->copySrcPhysAddr = 0;
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}
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return fault;
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#else
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return NoFault;
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#endif
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}
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Fault
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SimpleCPU::copy(Addr dest)
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{
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#if 0
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static bool no_warn = true;
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int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
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// Only support block sizes of 64 atm.
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assert(blk_size == 64);
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uint8_t data[blk_size];
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//assert(cpuXC->copySrcAddr);
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int offset = dest & (blk_size - 1);
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// Make sure block doesn't span page
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if (no_warn &&
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(dest & PageMask) != ((dest + blk_size) & PageMask) &&
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(dest >> 40) != 0xfffffc) {
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no_warn = false;
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warn("Copied block destination spans pages %x. ", dest);
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}
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memReq->reset(dest & ~(blk_size -1), blk_size);
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// translate to physical address
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Fault fault = cpuXC->translateDataWriteReq(req);
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if (fault == NoFault) {
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Addr dest_addr = memReq->paddr + offset;
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// Need to read straight from memory since we have more than 8 bytes.
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memReq->paddr = cpuXC->copySrcPhysAddr;
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cpuXC->mem->read(memReq, data);
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memReq->paddr = dest_addr;
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cpuXC->mem->write(memReq, data);
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if (dcacheInterface) {
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memReq->cmd = Copy;
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memReq->completionEvent = NULL;
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memReq->paddr = cpuXC->copySrcPhysAddr;
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memReq->dest = dest_addr;
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memReq->size = 64;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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dcacheInterface->access(memReq);
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}
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}
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else
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assert(!fault->isAlignmentFault());
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return fault;
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#else
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panic("copy not implemented");
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return NoFault;
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#endif
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}
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// precise architected memory state accessor macros
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template <class T>
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Fault
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SimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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if (status() == DcacheWaitResponse || status() == DcacheWaitSwitch) {
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// Fault fault = xc->read(memReq,data);
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// Not sure what to check for no fault...
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if (data_read_pkt->result == Success) {
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memcpy(&data, data_read_pkt->data, sizeof(T));
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}
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if (traceData) {
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traceData->setAddr(addr);
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}
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// @todo: Figure out a way to create a Fault from the packet result.
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return NoFault;
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}
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// memReq->reset(addr, sizeof(T), flags);
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#if SIMPLE_CPU_MEM_TIMING
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CpuRequest *data_read_req = new CpuRequest;
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#endif
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data_read_req->vaddr = addr;
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data_read_req->size = sizeof(T);
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data_read_req->flags = flags;
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data_read_req->time = curTick;
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// translate to physical address
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Fault fault = cpuXC->translateDataReadReq(data_read_req);
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// Now do the access.
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if (fault == NoFault) {
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#if SIMPLE_CPU_MEM_TIMING
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data_read_pkt = new Packet;
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data_read_pkt->cmd = Read;
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data_read_pkt->req = data_read_req;
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data_read_pkt->data = new uint8_t[8];
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#endif
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data_read_pkt->addr = data_read_req->paddr;
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data_read_pkt->size = sizeof(T);
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sendDcacheRequest(data_read_pkt);
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#if SIMPLE_CPU_MEM_IMMEDIATE
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// Need to find a way to not duplicate code above.
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if (data_read_pkt->result == Success) {
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memcpy(&data, data_read_pkt->data, sizeof(T));
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}
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if (traceData) {
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traceData->setAddr(addr);
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}
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// @todo: Figure out a way to create a Fault from the packet result.
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return NoFault;
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#endif
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}
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/*
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memReq->cmd = Read;
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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memReq->flags &= ~INST_READ;
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MemAccessResult result = dcacheInterface->access(memReq);
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// Ugly hack to get an event scheduled *only* if the access is
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// a miss. We really should add first-class support for this
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// at some point.
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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memReq->completionEvent = &cacheCompletionEvent;
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lastDcacheStall = curTick;
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unscheduleTickEvent();
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_status = DcacheMissStall;
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} else {
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// do functional access
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fault = cpuXC->read(memReq, data);
|
|
|
|
}
|
|
} else if(fault == NoFault) {
|
|
// do functional access
|
|
fault = cpuXC->read(memReq, data);
|
|
|
|
}
|
|
*/
|
|
// This will need a new way to tell if it has a dcache attached.
|
|
if (data_read_req->flags & UNCACHEABLE)
|
|
recordEvent("Uncached Read");
|
|
|
|
return fault;
|
|
}
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::read(Addr addr, double &data, unsigned flags)
|
|
{
|
|
return read(addr, *(uint64_t*)&data, flags);
|
|
}
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::read(Addr addr, float &data, unsigned flags)
|
|
{
|
|
return read(addr, *(uint32_t*)&data, flags);
|
|
}
|
|
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
|
|
{
|
|
return read(addr, (uint32_t&)data, flags);
|
|
}
|
|
|
|
|
|
template <class T>
|
|
Fault
|
|
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
data_write_req->vaddr = addr;
|
|
data_write_req->time = curTick;
|
|
data_write_req->size = sizeof(T);
|
|
data_write_req->flags = flags;
|
|
|
|
// translate to physical address
|
|
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
|
|
// Now do the access.
|
|
if (fault == NoFault) {
|
|
#if SIMPLE_CPU_MEM_TIMING
|
|
data_write_pkt = new Packet;
|
|
data_write_pkt->cmd = Write;
|
|
data_write_pkt->req = data_write_req;
|
|
data_write_pkt->data = new uint8_t[64];
|
|
memcpy(data_write_pkt->data, &data, sizeof(T));
|
|
#else
|
|
data_write_pkt->data = (uint8_t *)&data;
|
|
#endif
|
|
data_write_pkt->addr = data_write_req->paddr;
|
|
data_write_pkt->size = sizeof(T);
|
|
|
|
sendDcacheRequest(data_write_pkt);
|
|
}
|
|
|
|
/*
|
|
// do functional access
|
|
if (fault == NoFault)
|
|
fault = cpuXC->write(memReq, data);
|
|
|
|
if (fault == NoFault && dcacheInterface) {
|
|
memReq->cmd = Write;
|
|
memcpy(memReq->data,(uint8_t *)&data,memReq->size);
|
|
memReq->completionEvent = NULL;
|
|
memReq->time = curTick;
|
|
memReq->flags &= ~INST_READ;
|
|
MemAccessResult result = dcacheInterface->access(memReq);
|
|
|
|
// Ugly hack to get an event scheduled *only* if the access is
|
|
// a miss. We really should add first-class support for this
|
|
// at some point.
|
|
if (result != MA_HIT && dcacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastDcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = DcacheMissStall;
|
|
}
|
|
}
|
|
*/
|
|
if (res && (fault == NoFault))
|
|
*res = data_write_pkt->result;
|
|
|
|
// This will need a new way to tell if it's hooked up to a cache or not.
|
|
if (data_write_req->flags & UNCACHEABLE)
|
|
recordEvent("Uncached Write");
|
|
|
|
// If the write needs to have a fault on the access, consider calling
|
|
// changeStatus() and changing it to "bad addr write" or something.
|
|
return fault;
|
|
}
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
template
|
|
Fault
|
|
SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write(*(uint64_t*)&data, addr, flags, res);
|
|
}
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write(*(uint32_t*)&data, addr, flags, res);
|
|
}
|
|
|
|
|
|
template<>
|
|
Fault
|
|
SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
return write((uint32_t)data, addr, flags, res);
|
|
}
|
|
|
|
|
|
#if FULL_SYSTEM
|
|
Addr
|
|
SimpleCPU::dbg_vtophys(Addr addr)
|
|
{
|
|
return vtophys(xcProxy, addr);
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
void
|
|
SimpleCPU::sendIcacheRequest(Packet *pkt)
|
|
{
|
|
assert(!tickEvent.scheduled());
|
|
#if SIMPLE_CPU_MEM_TIMING
|
|
retry_pkt = pkt;
|
|
bool success = icachePort.sendTiming(*pkt);
|
|
|
|
unscheduleTickEvent();
|
|
|
|
lastIcacheStall = curTick;
|
|
|
|
if (!success) {
|
|
// Need to wait for retry
|
|
_status = IcacheRetry;
|
|
} else {
|
|
// Need to wait for cache to respond
|
|
_status = IcacheWaitResponse;
|
|
}
|
|
#elif SIMPLE_CPU_MEM_ATOMIC
|
|
Tick latency = icachePort.sendAtomic(*pkt);
|
|
|
|
unscheduleTickEvent();
|
|
scheduleTickEvent(latency);
|
|
|
|
// Note that Icache miss cycles will be incorrect. Unless
|
|
// we check the status of the packet sent (is this valid?),
|
|
// we won't know if the latency is a hit or a miss.
|
|
icacheStallCycles += latency;
|
|
|
|
_status = IcacheAccessComplete;
|
|
#elif SIMPLE_CPU_MEM_IMMEDIATE
|
|
icachePort.sendAtomic(*pkt);
|
|
#else
|
|
#error "SimpleCPU has no mem model set"
|
|
#endif
|
|
}
|
|
|
|
void
|
|
SimpleCPU::sendDcacheRequest(Packet *pkt)
|
|
{
|
|
assert(!tickEvent.scheduled());
|
|
#if SIMPLE_CPU_MEM_TIMING
|
|
unscheduleTickEvent();
|
|
|
|
retry_pkt = pkt;
|
|
bool success = dcachePort.sendTiming(*pkt);
|
|
|
|
lastDcacheStall = curTick;
|
|
|
|
if (!success) {
|
|
_status = DcacheRetry;
|
|
} else {
|
|
_status = DcacheWaitResponse;
|
|
}
|
|
#elif SIMPLE_CPU_MEM_ATOMIC
|
|
unscheduleTickEvent();
|
|
|
|
Tick latency = dcachePort.sendAtomic(*pkt);
|
|
|
|
scheduleTickEvent(latency);
|
|
|
|
// Note that Dcache miss cycles will be incorrect. Unless
|
|
// we check the status of the packet sent (is this valid?),
|
|
// we won't know if the latency is a hit or a miss.
|
|
dcacheStallCycles += latency;
|
|
#elif SIMPLE_CPU_MEM_IMMEDIATE
|
|
dcachePort.sendAtomic(*pkt);
|
|
#else
|
|
#error "SimpleCPU has no mem model set"
|
|
#endif
|
|
}
|
|
|
|
void
|
|
SimpleCPU::processResponse(Packet &response)
|
|
{
|
|
assert(SIMPLE_CPU_MEM_TIMING);
|
|
|
|
// For what things is the CPU the consumer of the packet it sent
|
|
// out? This may create a memory leak if that's the case and it's
|
|
// expected of the SimpleCPU to delete its own packet.
|
|
Packet *pkt = &response;
|
|
|
|
switch (status()) {
|
|
case IcacheWaitResponse:
|
|
icacheStallCycles += curTick - lastIcacheStall;
|
|
|
|
_status = IcacheAccessComplete;
|
|
scheduleTickEvent(1);
|
|
|
|
// Copy the icache data into the instruction itself.
|
|
memcpy(&inst, pkt->data, sizeof(inst));
|
|
|
|
delete pkt;
|
|
break;
|
|
case DcacheWaitResponse:
|
|
if (pkt->cmd == Read) {
|
|
curStaticInst->execute(this,traceData);
|
|
if (traceData)
|
|
traceData->finalize();
|
|
}
|
|
|
|
delete pkt;
|
|
|
|
dcacheStallCycles += curTick - lastDcacheStall;
|
|
_status = Running;
|
|
scheduleTickEvent(1);
|
|
break;
|
|
case DcacheWaitSwitch:
|
|
if (pkt->cmd == Read) {
|
|
curStaticInst->execute(this,traceData);
|
|
if (traceData)
|
|
traceData->finalize();
|
|
}
|
|
|
|
delete pkt;
|
|
|
|
_status = SwitchedOut;
|
|
sampler->signalSwitched();
|
|
case SwitchedOut:
|
|
// If this CPU has been switched out due to sampling/warm-up,
|
|
// ignore any further status changes (e.g., due to cache
|
|
// misses outstanding at the time of the switch).
|
|
delete pkt;
|
|
|
|
return;
|
|
default:
|
|
panic("SimpleCPU::processCacheCompletion: bad state");
|
|
break;
|
|
}
|
|
}
|
|
|
|
Packet *
|
|
SimpleCPU::processRetry()
|
|
{
|
|
#if SIMPLE_CPU_MEM_TIMING
|
|
switch(status()) {
|
|
case IcacheRetry:
|
|
icacheRetryCycles += curTick - lastIcacheStall;
|
|
return retry_pkt;
|
|
break;
|
|
case DcacheRetry:
|
|
dcacheRetryCycles += curTick - lastDcacheStall;
|
|
return retry_pkt;
|
|
break;
|
|
default:
|
|
panic("SimpleCPU::processRetry: bad state");
|
|
break;
|
|
}
|
|
#else
|
|
panic("shouldn't be here");
|
|
#endif
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
void
|
|
SimpleCPU::post_interrupt(int int_num, int index)
|
|
{
|
|
BaseCPU::post_interrupt(int_num, index);
|
|
|
|
if (cpuXC->status() == ExecContext::Suspended) {
|
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
|
cpuXC->activate();
|
|
}
|
|
}
|
|
#endif // FULL_SYSTEM
|
|
|
|
/* start simulation, program loaded, processor precise state initialized */
|
|
void
|
|
SimpleCPU::tick()
|
|
{
|
|
DPRINTF(SimpleCPU,"\n\n");
|
|
|
|
numCycles++;
|
|
|
|
traceData = NULL;
|
|
|
|
Fault fault = NoFault;
|
|
|
|
#if FULL_SYSTEM
|
|
if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
|
|
status() != IcacheAccessComplete) {
|
|
int ipl = 0;
|
|
int summary = 0;
|
|
checkInterrupts = false;
|
|
|
|
if (cpuXC->readMiscReg(IPR_SIRR)) {
|
|
for (int i = INTLEVEL_SOFTWARE_MIN;
|
|
i < INTLEVEL_SOFTWARE_MAX; i++) {
|
|
if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
}
|
|
|
|
uint64_t interrupts = cpuXC->cpu->intr_status();
|
|
for (int i = INTLEVEL_EXTERNAL_MIN;
|
|
i < INTLEVEL_EXTERNAL_MAX; i++) {
|
|
if (interrupts & (ULL(1) << i)) {
|
|
// See table 4-19 of 21164 hardware reference
|
|
ipl = i;
|
|
summary |= (ULL(1) << i);
|
|
}
|
|
}
|
|
|
|
if (cpuXC->readMiscReg(IPR_ASTRR))
|
|
panic("asynchronous traps not implemented\n");
|
|
|
|
if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) {
|
|
cpuXC->setMiscReg(IPR_ISR, summary);
|
|
cpuXC->setMiscReg(IPR_INTID, ipl);
|
|
|
|
Fault(new InterruptFault)->invoke(xcProxy);
|
|
|
|
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
|
|
cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
// maintain $r0 semantics
|
|
cpuXC->setIntReg(ZeroReg, 0);
|
|
#if THE_ISA == ALPHA_ISA
|
|
cpuXC->setFloatReg(ZeroReg, 0.0);
|
|
#endif // ALPHA_ISA
|
|
|
|
if (status() == IcacheAccessComplete) {
|
|
// We've already fetched an instruction and were stalled on an
|
|
// I-cache miss. No need to fetch it again.
|
|
|
|
// Set status to running; tick event will get rescheduled if
|
|
// necessary at end of tick() function.
|
|
_status = Running;
|
|
} else {
|
|
// Try to fetch an instruction
|
|
|
|
// set up memory request for instruction fetch
|
|
#if FULL_SYSTEM
|
|
#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
|
|
#else
|
|
#define IFETCH_FLAGS(pc) 0
|
|
#endif
|
|
|
|
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
|
|
cpuXC->readNextPC(),cpuXC->readNextNPC());
|
|
|
|
#if SIMPLE_CPU_MEM_TIMING
|
|
CpuRequest *ifetch_req = new CpuRequest();
|
|
ifetch_req->size = sizeof(MachInst);
|
|
#endif
|
|
|
|
ifetch_req->vaddr = cpuXC->readPC() & ~3;
|
|
ifetch_req->time = curTick;
|
|
|
|
/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
|
|
IFETCH_FLAGS(xc->regs.pc));
|
|
*/
|
|
|
|
fault = cpuXC->translateInstReq(ifetch_req);
|
|
|
|
if (fault == NoFault) {
|
|
#if SIMPLE_CPU_MEM_TIMING
|
|
Packet *ifetch_pkt = new Packet;
|
|
ifetch_pkt->cmd = Read;
|
|
ifetch_pkt->data = (uint8_t *)&inst;
|
|
ifetch_pkt->req = ifetch_req;
|
|
ifetch_pkt->size = sizeof(MachInst);
|
|
#endif
|
|
ifetch_pkt->addr = ifetch_req->paddr;
|
|
|
|
sendIcacheRequest(ifetch_pkt);
|
|
#if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC
|
|
return;
|
|
#endif
|
|
/*
|
|
if (icacheInterface && fault == NoFault) {
|
|
memReq->completionEvent = NULL;
|
|
|
|
memReq->time = curTick;
|
|
memReq->flags |= INST_READ;
|
|
MemAccessResult result = icacheInterface->access(memReq);
|
|
|
|
// Ugly hack to get an event scheduled *only* if the access is
|
|
// a miss. We really should add first-class support for this
|
|
// at some point.
|
|
if (result != MA_HIT && icacheInterface->doEvents()) {
|
|
memReq->completionEvent = &cacheCompletionEvent;
|
|
lastIcacheStall = curTick;
|
|
unscheduleTickEvent();
|
|
_status = IcacheMissStall;
|
|
return;
|
|
}
|
|
}
|
|
*/
|
|
}
|
|
}
|
|
|
|
// If we've got a valid instruction (i.e., no fault on instruction
|
|
// fetch), then execute it.
|
|
if (fault == NoFault) {
|
|
|
|
// keep an instruction count
|
|
numInst++;
|
|
numInsts++;
|
|
|
|
// check for instruction-count-based events
|
|
comInstEventQueue[0]->serviceEvents(numInst);
|
|
|
|
// decode the instruction
|
|
inst = gtoh(inst);
|
|
curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
|
|
|
|
traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
|
|
cpuXC->readPC());
|
|
|
|
DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
|
|
curStaticInst->getName(),curStaticInst->getOpcode(), curStaticInst->machInst);
|
|
|
|
#if FULL_SYSTEM
|
|
cpuXC->setInst(inst);
|
|
#endif // FULL_SYSTEM
|
|
|
|
cpuXC->func_exe_inst++;
|
|
|
|
fault = curStaticInst->execute(this, traceData);
|
|
|
|
#if FULL_SYSTEM
|
|
if (system->kernelBinning->fnbin) {
|
|
assert(kernelStats);
|
|
system->kernelBinning->execute(xcProxy, inst);
|
|
}
|
|
|
|
if (cpuXC->profile) {
|
|
bool usermode =
|
|
(cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
|
|
cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
|
|
ProfileNode *node = cpuXC->profile->consume(xcProxy, inst);
|
|
if (node)
|
|
cpuXC->profileNode = node;
|
|
}
|
|
#endif
|
|
|
|
if (curStaticInst->isMemRef()) {
|
|
numMemRefs++;
|
|
}
|
|
|
|
if (curStaticInst->isLoad()) {
|
|
++numLoad;
|
|
comLoadEventQueue[0]->serviceEvents(numLoad);
|
|
}
|
|
|
|
// If we have a dcache miss, then we can't finialize the instruction
|
|
// trace yet because we want to populate it with the data later
|
|
if (traceData && (status() != DcacheWaitResponse)) {
|
|
traceData->finalize();
|
|
}
|
|
|
|
traceFunctions(cpuXC->readPC());
|
|
|
|
} // if (fault == NoFault)
|
|
|
|
if (fault != NoFault) {
|
|
#if FULL_SYSTEM
|
|
fault->invoke(xcProxy);
|
|
#else // !FULL_SYSTEM
|
|
fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
else {
|
|
#if THE_ISA == ALPHA_ISA
|
|
// go to the next instruction
|
|
cpuXC->setPC(cpuXC->readNextPC());
|
|
cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
|
|
#else
|
|
// go to the next instruction
|
|
cpuXC->setPC(cpuXC->readNextPC());
|
|
cpuXC->setNextPC(cpuXC->readNextNPC());
|
|
cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
|
|
#endif
|
|
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
Addr oldpc;
|
|
do {
|
|
oldpc = cpuXC->readPC();
|
|
system->pcEventQueue.service(xcProxy);
|
|
} while (oldpc != cpuXC->readPC());
|
|
#endif
|
|
|
|
assert(status() == Running ||
|
|
status() == Idle ||
|
|
status() == DcacheWaitResponse);
|
|
|
|
if (status() == Running && !tickEvent.scheduled())
|
|
tickEvent.schedule(curTick + cycles(1));
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// SimpleCPU Simulation Object
|
|
//
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
Param<Counter> max_insts_any_thread;
|
|
Param<Counter> max_insts_all_threads;
|
|
Param<Counter> max_loads_any_thread;
|
|
Param<Counter> max_loads_all_threads;
|
|
|
|
#if FULL_SYSTEM
|
|
SimObjectParam<AlphaITB *> itb;
|
|
SimObjectParam<AlphaDTB *> dtb;
|
|
SimObjectParam<System *> system;
|
|
Param<int> cpu_id;
|
|
Param<Tick> profile;
|
|
#else
|
|
SimObjectParam<MemObject *> mem;
|
|
SimObjectParam<Process *> workload;
|
|
#endif // FULL_SYSTEM
|
|
|
|
Param<int> clock;
|
|
|
|
Param<bool> defer_registration;
|
|
Param<int> width;
|
|
Param<bool> function_trace;
|
|
Param<Tick> function_trace_start;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
INIT_PARAM(max_insts_any_thread,
|
|
"terminate when any thread reaches this inst count"),
|
|
INIT_PARAM(max_insts_all_threads,
|
|
"terminate when all threads have reached this inst count"),
|
|
INIT_PARAM(max_loads_any_thread,
|
|
"terminate when any thread reaches this load count"),
|
|
INIT_PARAM(max_loads_all_threads,
|
|
"terminate when all threads have reached this load count"),
|
|
|
|
#if FULL_SYSTEM
|
|
INIT_PARAM(itb, "Instruction TLB"),
|
|
INIT_PARAM(dtb, "Data TLB"),
|
|
INIT_PARAM(system, "system object"),
|
|
INIT_PARAM(cpu_id, "processor ID"),
|
|
INIT_PARAM(profile, ""),
|
|
#else
|
|
INIT_PARAM(mem, "memory"),
|
|
INIT_PARAM(workload, "processes to run"),
|
|
#endif // FULL_SYSTEM
|
|
|
|
INIT_PARAM(clock, "clock speed"),
|
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
|
INIT_PARAM(width, "cpu width"),
|
|
INIT_PARAM(function_trace, "Enable function trace"),
|
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
|
|
|
|
|
|
CREATE_SIM_OBJECT(SimpleCPU)
|
|
{
|
|
SimpleCPU::Params *params = new SimpleCPU::Params();
|
|
params->name = getInstanceName();
|
|
params->numberOfThreads = 1;
|
|
params->max_insts_any_thread = max_insts_any_thread;
|
|
params->max_insts_all_threads = max_insts_all_threads;
|
|
params->max_loads_any_thread = max_loads_any_thread;
|
|
params->max_loads_all_threads = max_loads_all_threads;
|
|
params->deferRegistration = defer_registration;
|
|
params->clock = clock;
|
|
params->functionTrace = function_trace;
|
|
params->functionTraceStart = function_trace_start;
|
|
params->width = width;
|
|
|
|
#if FULL_SYSTEM
|
|
params->itb = itb;
|
|
params->dtb = dtb;
|
|
params->system = system;
|
|
params->cpu_id = cpu_id;
|
|
params->profile = profile;
|
|
#else
|
|
params->mem = mem;
|
|
params->process = workload;
|
|
#endif
|
|
|
|
SimpleCPU *cpu = new SimpleCPU(params);
|
|
return cpu;
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
|
|
|