82f2ae56ed
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007
617 lines
20 KiB
C++
617 lines
20 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// Remove this later; used only for debugging.
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#define OPCODE(X) (X >> 26) & 0x3f
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#include "arch/isa_traits.hh"
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#include "sim/byteswap.hh"
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#include "cpu/exetrace.hh"
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#include "mem/base_mem.hh"
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#include "mem/mem_interface.hh"
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#include "mem/mem_req.hh"
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#include "cpu/o3/fetch.hh"
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#include "sim/root.hh"
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template<class Impl>
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SimpleFetch<Impl>::CacheCompletionEvent
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::CacheCompletionEvent(SimpleFetch *_fetch)
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: Event(&mainEventQueue),
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fetch(_fetch)
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{
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::CacheCompletionEvent::process()
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{
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fetch->processCacheCompletion();
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}
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template<class Impl>
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const char *
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SimpleFetch<Impl>::CacheCompletionEvent::description()
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{
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return "SimpleFetch cache completion event";
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}
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template<class Impl>
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SimpleFetch<Impl>::SimpleFetch(Params ¶ms)
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: icacheInterface(params.icacheInterface),
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branchPred(params),
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decodeToFetchDelay(params.decodeToFetchDelay),
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renameToFetchDelay(params.renameToFetchDelay),
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iewToFetchDelay(params.iewToFetchDelay),
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commitToFetchDelay(params.commitToFetchDelay),
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fetchWidth(params.fetchWidth)
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{
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DPRINTF(Fetch, "Fetch: Fetch constructor called\n");
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// Set status to idle.
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_status = Idle;
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// Create a new memory request.
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memReq = new MemReq();
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// Not sure of this parameter. I think it should be based on the
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// thread number.
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#if !FULL_SYSTEM
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memReq->asid = 0;
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#else
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memReq->asid = 0;
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#endif // FULL_SYSTEM
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memReq->data = new uint8_t[64];
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// Size of cache block.
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cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
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// Create mask to get rid of offset bits.
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cacheBlkMask = (cacheBlkSize - 1);
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// Get the size of an instruction.
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instSize = sizeof(MachInst);
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// Create space to store a cache line.
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cacheData = new uint8_t[cacheBlkSize];
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}
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template <class Impl>
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void
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SimpleFetch<Impl>::regStats()
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{
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icacheStallCycles
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.name(name() + ".icacheStallCycles")
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.desc("Number of cycles fetch is stalled on an Icache miss")
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.prereq(icacheStallCycles);
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fetchedInsts
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.name(name() + ".fetchedInsts")
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.desc("Number of instructions fetch has processed")
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.prereq(fetchedInsts);
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predictedBranches
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.name(name() + ".predictedBranches")
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.desc("Number of branches that fetch has predicted taken")
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.prereq(predictedBranches);
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fetchCycles
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.name(name() + ".fetchCycles")
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.desc("Number of cycles fetch has run and was not squashing or"
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" blocked")
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.prereq(fetchCycles);
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fetchSquashCycles
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.name(name() + ".fetchSquashCycles")
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.desc("Number of cycles fetch has spent squashing")
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.prereq(fetchSquashCycles);
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fetchBlockedCycles
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.name(name() + ".fetchBlockedCycles")
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.desc("Number of cycles fetch has spent blocked")
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.prereq(fetchBlockedCycles);
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fetchedCacheLines
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.name(name() + ".fetchedCacheLines")
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.desc("Number of cache lines fetched")
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.prereq(fetchedCacheLines);
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fetch_nisn_dist
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.init(/* base value */ 0,
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/* last value */ fetchWidth,
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/* bucket size */ 1)
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.name(name() + ".FETCH:rate_dist")
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.desc("Number of instructions fetched each cycle (Total)")
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.flags(Stats::pdf)
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;
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branchPred.regStats();
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::setCPU(FullCPU *cpu_ptr)
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{
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DPRINTF(Fetch, "Fetch: Setting the CPU pointer.\n");
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cpu = cpu_ptr;
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// This line will be removed eventually.
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memReq->xc = cpu->xcBase();
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
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{
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DPRINTF(Fetch, "Fetch: Setting the time buffer pointer.\n");
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timeBuffer = time_buffer;
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// Create wires to get information from proper places in time buffer.
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fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
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fromRename = timeBuffer->getWire(-renameToFetchDelay);
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fromIEW = timeBuffer->getWire(-iewToFetchDelay);
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fromCommit = timeBuffer->getWire(-commitToFetchDelay);
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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{
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DPRINTF(Fetch, "Fetch: Setting the fetch queue pointer.\n");
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fetchQueue = fq_ptr;
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// Create wire to write information to proper place in fetch queue.
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toDecode = fetchQueue->getWire(0);
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::processCacheCompletion()
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{
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DPRINTF(Fetch, "Fetch: Waking up from cache miss.\n");
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// Only change the status if it's still waiting on the icache access
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// to return.
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// Can keep track of how many cache accesses go unused due to
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// misspeculation here.
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if (_status == IcacheMissStall)
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_status = IcacheMissComplete;
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}
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template <class Impl>
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bool
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SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
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{
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// Do branch prediction check here.
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// A bit of a misnomer...next_PC is actually the current PC until
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// this function updates it.
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bool predict_taken;
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if (!inst->isControl()) {
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next_PC = next_PC + instSize;
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inst->setPredTarg(next_PC);
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return false;
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}
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predict_taken = branchPred.predict(inst, next_PC);
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if (predict_taken) {
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++predictedBranches;
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}
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return predict_taken;
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}
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template <class Impl>
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Fault
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SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
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{
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// Check if the instruction exists within the cache.
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// If it does, then proceed on to read the instruction and the rest
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// of the instructions in the cache line until either the end of the
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// cache line or a predicted taken branch is encountered.
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#if FULL_SYSTEM
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// Flag to say whether or not address is physical addr.
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unsigned flags = cpu->inPalMode() ? PHYSICAL : 0;
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#else
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unsigned flags = 0;
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#endif // FULL_SYSTEM
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Fault fault = No_Fault;
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// Align the fetch PC so it's at the start of a cache block.
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fetch_PC = icacheBlockAlignPC(fetch_PC);
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// Setup the memReq to do a read of the first isntruction's address.
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// Set the appropriate read size and flags as well.
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memReq->cmd = Read;
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memReq->reset(fetch_PC, cacheBlkSize, flags);
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// Translate the instruction request.
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// Should this function be
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// in the CPU class ? Probably...ITB/DTB should exist within the
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// CPU.
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fault = cpu->translateInstReq(memReq);
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// In the case of faults, the fetch stage may need to stall and wait
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// on what caused the fetch (ITB or Icache miss).
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// If translation was successful, attempt to read the first
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// instruction.
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if (fault == No_Fault) {
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DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
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fault = cpu->mem->read(memReq, cacheData);
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// This read may change when the mem interface changes.
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fetchedCacheLines++;
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}
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// Now do the timing access to see whether or not the instruction
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// exists within the cache.
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if (icacheInterface && fault == No_Fault) {
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DPRINTF(Fetch, "Fetch: Doing timing memory access.\n");
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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MemAccessResult result = icacheInterface->access(memReq);
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// If the cache missed (in this model functional and timing
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// memories are different), then schedule an event to wake
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// up this stage once the cache miss completes.
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if (result != MA_HIT && icacheInterface->doEvents()) {
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memReq->completionEvent = new CacheCompletionEvent(this);
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// How does current model work as far as individual
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// stages scheduling/unscheduling?
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// Perhaps have only the main CPU scheduled/unscheduled,
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// and have it choose what stages to run appropriately.
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DPRINTF(Fetch, "Fetch: Stalling due to icache miss.\n");
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_status = IcacheMissStall;
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}
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}
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return fault;
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}
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template <class Impl>
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inline void
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SimpleFetch<Impl>::doSquash(const Addr &new_PC)
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{
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DPRINTF(Fetch, "Fetch: Squashing, setting PC to: %#x.\n", new_PC);
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cpu->setNextPC(new_PC + instSize);
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cpu->setPC(new_PC);
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// Clear the icache miss if it's outstanding.
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if (_status == IcacheMissStall && icacheInterface) {
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DPRINTF(Fetch, "Fetch: Squashing outstanding Icache miss.\n");
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// @todo: Use an actual thread number here.
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icacheInterface->squash(0);
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}
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_status = Squashing;
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++fetchSquashCycles;
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::squashFromDecode(const Addr &new_PC,
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const InstSeqNum &seq_num)
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{
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DPRINTF(Fetch, "Fetch: Squashing from decode.\n");
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doSquash(new_PC);
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// Tell the CPU to remove any instructions that are in flight between
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// fetch and decode.
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cpu->removeInstsUntil(seq_num);
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}
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template <class Impl>
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void
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SimpleFetch<Impl>::squash(const Addr &new_PC)
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{
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DPRINTF(Fetch, "Fetch: Squash from commit.\n");
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doSquash(new_PC);
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// Tell the CPU to remove any instructions that are not in the ROB.
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cpu->removeInstsNotInROB();
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::tick()
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{
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// Check squash signals from commit.
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if (fromCommit->commitInfo.squash) {
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DPRINTF(Fetch, "Fetch: Squashing instructions due to squash "
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"from commit.\n");
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// In any case, squash.
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squash(fromCommit->commitInfo.nextPC);
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// Also check if there's a mispredict that happened.
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if (fromCommit->commitInfo.branchMispredict) {
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branchPred.squash(fromCommit->commitInfo.doneSeqNum,
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fromCommit->commitInfo.nextPC,
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fromCommit->commitInfo.branchTaken);
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} else {
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branchPred.squash(fromCommit->commitInfo.doneSeqNum);
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}
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return;
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} else if (fromCommit->commitInfo.doneSeqNum) {
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// Update the branch predictor if it wasn't a squashed instruction
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// that was braodcasted.
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branchPred.update(fromCommit->commitInfo.doneSeqNum);
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}
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// Check ROB squash signals from commit.
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if (fromCommit->commitInfo.robSquashing) {
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DPRINTF(Fetch, "Fetch: ROB is still squashing.\n");
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// Continue to squash.
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_status = Squashing;
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++fetchSquashCycles;
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return;
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}
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// Check squash signals from decode.
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if (fromDecode->decodeInfo.squash) {
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DPRINTF(Fetch, "Fetch: Squashing instructions due to squash "
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"from decode.\n");
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// Update the branch predictor.
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if (fromDecode->decodeInfo.branchMispredict) {
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branchPred.squash(fromDecode->decodeInfo.doneSeqNum,
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fromDecode->decodeInfo.nextPC,
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fromDecode->decodeInfo.branchTaken);
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} else {
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branchPred.squash(fromDecode->decodeInfo.doneSeqNum);
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}
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if (_status != Squashing) {
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// Squash unless we're already squashing?
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squashFromDecode(fromDecode->decodeInfo.nextPC,
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fromDecode->decodeInfo.doneSeqNum);
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return;
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}
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}
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// Check if any of the stall signals are high.
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if (fromDecode->decodeInfo.stall ||
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fromRename->renameInfo.stall ||
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fromIEW->iewInfo.stall ||
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fromCommit->commitInfo.stall)
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{
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// Block stage, regardless of current status.
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DPRINTF(Fetch, "Fetch: Stalling stage.\n");
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DPRINTF(Fetch, "Fetch: Statuses: Decode: %i Rename: %i IEW: %i "
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"Commit: %i\n",
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fromDecode->decodeInfo.stall,
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fromRename->renameInfo.stall,
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fromIEW->iewInfo.stall,
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fromCommit->commitInfo.stall);
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_status = Blocked;
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++fetchBlockedCycles;
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return;
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} else if (_status == Blocked) {
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// Unblock stage if status is currently blocked and none of the
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// stall signals are being held high.
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_status = Running;
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++fetchBlockedCycles;
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return;
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}
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// If fetch has reached this point, then there are no squash signals
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// still being held high. Check if fetch is in the squashing state;
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// if so, fetch can switch to running.
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// Similarly, there are no blocked signals still being held high.
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// Check if fetch is in the blocked state; if so, fetch can switch to
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// running.
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if (_status == Squashing) {
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DPRINTF(Fetch, "Fetch: Done squashing, switching to running.\n");
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// Switch status to running
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_status = Running;
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++fetchCycles;
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fetch();
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} else if (_status != IcacheMissStall) {
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DPRINTF(Fetch, "Fetch: Running stage.\n");
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++fetchCycles;
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fetch();
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}
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}
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template<class Impl>
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void
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SimpleFetch<Impl>::fetch()
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{
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//////////////////////////////////////////
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// Start actual fetch
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//////////////////////////////////////////
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// The current PC.
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Addr fetch_PC = cpu->readPC();
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// Fault code for memory access.
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Fault fault = No_Fault;
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// If returning from the delay of a cache miss, then update the status
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// to running, otherwise do the cache access. Possibly move this up
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// to tick() function.
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if (_status == IcacheMissComplete) {
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DPRINTF(Fetch, "Fetch: Icache miss is complete.\n");
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// Reset the completion event to NULL.
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memReq->completionEvent = NULL;
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_status = Running;
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} else {
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DPRINTF(Fetch, "Fetch: Attempting to translate and read "
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"instruction, starting at PC %08p.\n",
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fetch_PC);
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fault = fetchCacheLine(fetch_PC);
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}
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// If we had a stall due to an icache miss, then return. It'd
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// be nicer if this were handled through the kind of fault that
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// is returned by the function.
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if (_status == IcacheMissStall) {
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return;
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}
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// As far as timing goes, the CPU will need to send an event through
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// the MemReq in order to be woken up once the memory access completes.
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// Probably have a status on a per thread basis so each thread can
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// block independently and be woken up independently.
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Addr next_PC = fetch_PC;
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InstSeqNum inst_seq;
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MachInst inst;
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unsigned offset = fetch_PC & cacheBlkMask;
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unsigned fetched;
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if (fault == No_Fault) {
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// If the read of the first instruction was successful, then grab the
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// instructions from the rest of the cache line and put them into the
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// queue heading to decode.
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DPRINTF(Fetch, "Fetch: Adding instructions to queue to decode.\n");
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//////////////////////////
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// Fetch first instruction
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//////////////////////////
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// Need to keep track of whether or not a predicted branch
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// ended this fetch block.
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bool predicted_branch = false;
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|
|
for (fetched = 0;
|
|
offset < cacheBlkSize &&
|
|
fetched < fetchWidth &&
|
|
!predicted_branch;
|
|
++fetched)
|
|
{
|
|
|
|
// Get a sequence number.
|
|
inst_seq = cpu->getAndIncrementInstSeq();
|
|
|
|
// Make sure this is a valid index.
|
|
assert(offset <= cacheBlkSize - instSize);
|
|
|
|
// Get the instruction from the array of the cache line.
|
|
inst = gtoh(*reinterpret_cast<MachInst *>
|
|
(&cacheData[offset]));
|
|
|
|
// Create a new DynInst from the instruction fetched.
|
|
DynInstPtr instruction = new DynInst(inst, fetch_PC, next_PC,
|
|
inst_seq, cpu);
|
|
|
|
DPRINTF(Fetch, "Fetch: Instruction %i created, with PC %#x\n",
|
|
inst_seq, instruction->readPC());
|
|
|
|
DPRINTF(Fetch, "Fetch: Instruction opcode is: %03p\n",
|
|
OPCODE(inst));
|
|
|
|
instruction->traceData =
|
|
Trace::getInstRecord(curTick, cpu->xcBase(), cpu,
|
|
instruction->staticInst,
|
|
instruction->readPC(), 0);
|
|
|
|
predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
|
|
|
|
// Add instruction to the CPU's list of instructions.
|
|
cpu->addInst(instruction);
|
|
|
|
// Write the instruction to the first slot in the queue
|
|
// that heads to decode.
|
|
toDecode->insts[fetched] = instruction;
|
|
|
|
toDecode->size++;
|
|
|
|
// Increment stat of fetched instructions.
|
|
++fetchedInsts;
|
|
|
|
// Move to the next instruction, unless we have a branch.
|
|
fetch_PC = next_PC;
|
|
|
|
offset+= instSize;
|
|
}
|
|
|
|
fetch_nisn_dist.sample(fetched);
|
|
}
|
|
|
|
// Now that fetching is completed, update the PC to signify what the next
|
|
// cycle will be. Might want to move this to the beginning of this
|
|
// function so that the PC updates at the beginning of everything.
|
|
// Or might want to leave setting the PC to the main CPU, with fetch
|
|
// only changing the nextPC (will require correct determination of
|
|
// next PC).
|
|
if (fault == No_Fault) {
|
|
DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC);
|
|
cpu->setPC(next_PC);
|
|
cpu->setNextPC(next_PC + instSize);
|
|
} else {
|
|
// If the issue was an icache miss, then we can just return and
|
|
// wait until it is handled.
|
|
if (_status == IcacheMissStall) {
|
|
return;
|
|
}
|
|
|
|
// Handle the fault.
|
|
// This stage will not be able to continue until all the ROB
|
|
// slots are empty, at which point the fault can be handled.
|
|
// The only other way it can wake up is if a squash comes along
|
|
// and changes the PC. Not sure how to handle that case...perhaps
|
|
// have it handled by the upper level CPU class which peeks into the
|
|
// time buffer and sees if a squash comes along, in which case it
|
|
// changes the status.
|
|
|
|
DPRINTF(Fetch, "Fetch: Blocked, need to handle the trap.\n");
|
|
|
|
_status = Blocked;
|
|
#if FULL_SYSTEM
|
|
// cpu->trap(fault);
|
|
// Send a signal to the ROB indicating that there's a trap from the
|
|
// fetch stage that needs to be handled. Need to indicate that
|
|
// there's a fault, and the fault type.
|
|
#else // !FULL_SYSTEM
|
|
fatal("fault (%d) detected @ PC %08p", fault, cpu->readPC());
|
|
#endif // FULL_SYSTEM
|
|
}
|
|
}
|