82862e0e15
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA
--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a
125 lines
4.2 KiB
C++
125 lines
4.2 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Korey Sewell
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*/
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#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
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#define __ARCH_MIPS_ISA_TRAITS_HH__
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#include "arch/mips/types.hh"
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#include "sim/host.hh"
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namespace LittleEndianGuest {};
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#define TARGET_MIPS
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class StaticInstPtr;
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namespace MipsISA
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{
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using namespace LittleEndianGuest;
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StaticInstPtr decodeInst(ExtMachInst);
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// MIPS DOES a delay slot
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#define ISA_HAS_DELAY_SLOT 1
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const Addr PageShift = 13;
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const Addr PageBytes = ULL(1) << PageShift;
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const Addr PageMask = ~(PageBytes - 1);
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const Addr PageOffset = PageBytes - 1;
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// return a no-op instruction... used for instruction fetch faults
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const ExtMachInst NoopMachInst = 0x00000000;
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// Constants Related to the number of registers
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const int NumIntArchRegs = 32;
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const int NumIntSpecialRegs = 2;
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const int NumFloatArchRegs = 32;
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const int NumFloatSpecialRegs = 5;
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const int NumControlRegs = 265;
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const int NumInternalProcRegs = 0;
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const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
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const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
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const int NumMiscRegs = NumControlRegs;
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const int TotalNumRegs = NumIntRegs + NumFloatRegs +
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NumMiscRegs + 0/*NumInternalProcRegs*/;
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const int TotalDataRegs = NumIntRegs + NumFloatRegs;
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// Static instruction parameters
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const int MaxInstSrcRegs = 3;
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const int MaxInstDestRegs = 2;
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// semantically meaningful register indices
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const int ZeroReg = 0;
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const int AssemblerReg = 1;
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const int ReturnValueReg = 2;
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const int ReturnValueReg1 = 2;
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const int ReturnValueReg2 = 3;
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const int ArgumentReg0 = 4;
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const int ArgumentReg1 = 5;
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const int ArgumentReg2 = 6;
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const int ArgumentReg3 = 7;
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const int KernelReg0 = 26;
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const int KernelReg1 = 27;
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const int GlobalPointerReg = 28;
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const int StackPointerReg = 29;
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const int FramePointerReg = 30;
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const int ReturnAddressReg = 31;
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const int SyscallNumReg = ReturnValueReg1;
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const int SyscallPseudoReturnReg = ReturnValueReg1;
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const int SyscallSuccessReg = ArgumentReg3;
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const int LogVMPageSize = 13; // 8K bytes
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const int VMPageSize = (1 << LogVMPageSize);
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const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
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const int MachineBytes = 4;
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const int WordBytes = 4;
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const int HalfwordBytes = 2;
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const int ByteBytes = 1;
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// These help enumerate all the registers for dependence tracking.
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const int FP_Base_DepTag = 34;
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const int Ctrl_Base_DepTag = 257;
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const int ANNOTE_NONE = 0;
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const uint32_t ITOUCH_ANNOTE = 0xffffffff;
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};
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using namespace MipsISA;
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#endif // __ARCH_MIPS_ISA_TRAITS_HH__
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