225 lines
7.5 KiB
C++
225 lines
7.5 KiB
C++
/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/* @file
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* Register and structure descriptions for Intel's I/O AT DMA Engine
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*/
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#include "base/bitfield.hh"
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#include "sim/serialize.hh"
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namespace CopyEngineReg {
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// General Channel independant registers, 128 bytes starting at 0x00
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const uint32_t GEN_CHANCOUNT = 0x00;
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const uint32_t GEN_XFERCAP = 0x01;
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const uint32_t GEN_INTRCTRL = 0x03;
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const uint32_t GEN_ATTNSTATUS = 0x04;
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// Channel specific registers, each block is 128 bytes, starting at 0x80
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const uint32_t CHAN_CONTROL = 0x00;
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const uint32_t CHAN_STATUS = 0x04;
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const uint32_t CHAN_CHAINADDR = 0x0C;
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const uint32_t CHAN_CHAINADDR_LOW = 0x0C;
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const uint32_t CHAN_CHAINADDR_HIGH = 0x10;
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const uint32_t CHAN_COMMAND = 0x14;
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const uint32_t CHAN_CMPLNADDR = 0x18;
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const uint32_t CHAN_CMPLNADDR_LOW = 0x18;
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const uint32_t CHAN_CMPLNADDR_HIGH = 0x1C;
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const uint32_t CHAN_ERROR = 0x28;
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const uint32_t DESC_CTRL_INT_GEN = 0x00000001;
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const uint32_t DESC_CTRL_SRC_SN = 0x00000002;
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const uint32_t DESC_CTRL_DST_SN = 0x00000004;
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const uint32_t DESC_CTRL_CP_STS = 0x00000008;
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const uint32_t DESC_CTRL_FRAME = 0x00000010;
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const uint32_t DESC_CTRL_NULL = 0x00000020;
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struct DmaDesc {
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uint32_t len;
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uint32_t command;
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Addr src;
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Addr dest;
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Addr next;
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uint64_t reserved1;
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uint64_t reserved2;
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uint64_t user1;
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uint64_t user2;
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};
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#define ADD_FIELD8(NAME, OFFSET, BITS) \
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inline uint8_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
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inline void NAME(uint8_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
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#define ADD_FIELD16(NAME, OFFSET, BITS) \
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inline uint16_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
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inline void NAME(uint16_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
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#define ADD_FIELD32(NAME, OFFSET, BITS) \
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inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
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inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
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#define ADD_FIELD64(NAME, OFFSET, BITS) \
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inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
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inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
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template<class T>
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struct Reg {
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T _data;
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T operator()() { return _data; }
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const Reg<T> &operator=(T d) { _data = d; return *this;}
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bool operator==(T d) { return d == _data; }
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void operator()(T d) { _data = d; }
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Reg() { _data = 0; }
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void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(_data);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(_data);
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}
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};
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struct Regs {
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uint8_t chanCount;
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uint8_t xferCap;
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struct INTRCTRL : public Reg<uint8_t> { // 0x03
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using Reg<uint8_t>::operator =;
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ADD_FIELD8(master_int_enable,0,1);
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ADD_FIELD8(interrupt_status,1,1);
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ADD_FIELD8(interrupt,2,1);
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};
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INTRCTRL intrctrl;
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uint32_t attnStatus; // Read clears
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void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(chanCount);
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SERIALIZE_SCALAR(xferCap);
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paramOut(os, "intrctrl", intrctrl._data);
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SERIALIZE_SCALAR(attnStatus);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(chanCount);
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UNSERIALIZE_SCALAR(xferCap);
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paramIn(cp, section, "intrctrl", intrctrl._data);
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UNSERIALIZE_SCALAR(attnStatus);
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}
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};
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struct ChanRegs {
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struct CHANCTRL : public Reg<uint16_t> { // channelX + 0x00
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using Reg<uint16_t>::operator =;
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ADD_FIELD16(interrupt_disable,0,1);
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ADD_FIELD16(error_completion_enable, 2,1);
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ADD_FIELD16(any_error_abort_enable,3,1);
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ADD_FIELD16(error_int_enable,4,1);
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ADD_FIELD16(desc_addr_snoop_control,5,1);
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ADD_FIELD16(in_use, 8,1);
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};
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CHANCTRL ctrl;
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struct CHANSTS : public Reg<uint64_t> { // channelX + 0x04
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ADD_FIELD64(dma_transfer_status, 0, 3);
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ADD_FIELD64(unaffiliated_error, 3, 1);
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ADD_FIELD64(soft_error, 4, 1);
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ADD_FIELD64(compl_desc_addr, 6, 58);
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};
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CHANSTS status;
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uint64_t descChainAddr;
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struct CHANCMD : public Reg<uint8_t> { // channelX + 0x14
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ADD_FIELD8(start_dma,0,1);
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ADD_FIELD8(append_dma,1,1);
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ADD_FIELD8(suspend_dma,2,1);
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ADD_FIELD8(abort_dma,3,1);
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ADD_FIELD8(resume_dma,4,1);
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ADD_FIELD8(reset_dma,5,1);
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};
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CHANCMD command;
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uint64_t completionAddr;
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struct CHANERR : public Reg<uint32_t> { // channel X + 0x28
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ADD_FIELD32(source_addr_error,0,1);
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ADD_FIELD32(dest_addr_error,1,1);
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ADD_FIELD32(ndesc_addr_error,2,1);
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ADD_FIELD32(desc_error,3,1);
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ADD_FIELD32(chain_addr_error,4,1);
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ADD_FIELD32(chain_cmd_error,5,1);
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ADD_FIELD32(chipset_parity_error,6,1);
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ADD_FIELD32(dma_parity_error,7,1);
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ADD_FIELD32(read_data_error,8,1);
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ADD_FIELD32(write_data_error,9,1);
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ADD_FIELD32(desc_control_error,10,1);
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ADD_FIELD32(desc_len_error,11,1);
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ADD_FIELD32(completion_addr_error,12,1);
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ADD_FIELD32(interrupt_config_error,13,1);
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ADD_FIELD32(soft_error,14,1);
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ADD_FIELD32(unaffiliated_error,15,1);
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};
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CHANERR error;
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void serialize(std::ostream &os)
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{
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paramOut(os, "ctrl", ctrl._data);
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paramOut(os, "status", status._data);
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SERIALIZE_SCALAR(descChainAddr);
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paramOut(os, "command", command._data);
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SERIALIZE_SCALAR(completionAddr);
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paramOut(os, "error", error._data);
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}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{
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paramIn(cp, section, "ctrl", ctrl._data);
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paramIn(cp, section, "status", status._data);
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UNSERIALIZE_SCALAR(descChainAddr);
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paramIn(cp, section, "command", command._data);
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UNSERIALIZE_SCALAR(completionAddr);
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paramIn(cp, section, "error", error._data);
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}
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};
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} //namespace CopyEngineReg
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