c2271e301d
Faults that could potentially be routed to the hypervisor checked whether or not they were in a secure state without checking if security was enabled or not. This caused faults not to be routed correctly. This patch causes secure state checking to first ask if security is enabled. Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119
290 lines
9.7 KiB
C++
290 lines
9.7 KiB
C++
/*
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* Copyright (c) 2010, 2012-2013, 2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_INTERRUPT_HH__
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#define __ARCH_ARM_INTERRUPT_HH__
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#include "arch/arm/faults.hh"
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/miscregs.hh"
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#include "arch/arm/registers.hh"
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#include "arch/arm/utility.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Interrupt.hh"
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#include "params/ArmInterrupts.hh"
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#include "sim/sim_object.hh"
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namespace ArmISA
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{
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class Interrupts : public SimObject
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{
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private:
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BaseCPU * cpu;
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bool interrupts[NumInterruptTypes];
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uint64_t intStatus;
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public:
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void
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setCPU(BaseCPU * _cpu)
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{
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cpu = _cpu;
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}
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typedef ArmInterruptsParams Params;
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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Interrupts(Params * p) : SimObject(p), cpu(NULL)
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{
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clearAll();
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}
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void
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post(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptTypes)
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panic("int_num out of bounds\n");
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if (index != 0)
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panic("No support for other interrupt indexes\n");
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interrupts[int_num] = true;
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intStatus |= ULL(1) << int_num;
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}
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void
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clear(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptTypes)
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panic("int_num out of bounds\n");
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if (index != 0)
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panic("No support for other interrupt indexes\n");
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interrupts[int_num] = false;
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intStatus &= ~(ULL(1) << int_num);
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}
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void
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clearAll()
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{
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DPRINTF(Interrupt, "Interrupts all cleared\n");
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intStatus = 0;
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memset(interrupts, 0, sizeof(interrupts));
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}
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enum InterruptMask {
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INT_MASK_M, // masked (subject to PSTATE.{A,I,F} mask bit
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INT_MASK_T, // taken regardless of mask
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INT_MASK_P // pending
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};
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bool takeInt(ThreadContext *tc, InterruptTypes int_type) const;
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bool
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checkInterrupts(ThreadContext *tc) const
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{
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HCR hcr = tc->readMiscReg(MISCREG_HCR);
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if (!(intStatus || hcr.va || hcr.vi || hcr.vf))
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return false;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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bool isHypMode = cpsr.mode == MODE_HYP;
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bool isSecure = inSecureState(tc);
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bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
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bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
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bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
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if ( !(intStatus || (hcr.vi && allowVIrq) || (hcr.vf && allowVFiq) ||
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(hcr.va && allowVAbort)) )
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return false;
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bool take_irq = takeInt(tc, INT_IRQ);
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bool take_fiq = takeInt(tc, INT_FIQ);
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bool take_ea = takeInt(tc, INT_ABT);
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return ((interrupts[INT_IRQ] && take_irq) ||
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(interrupts[INT_FIQ] && take_fiq) ||
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(interrupts[INT_ABT] && take_ea) ||
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((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq) ||
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((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq) ||
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(hcr.va && allowVAbort) ||
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(interrupts[INT_RST]) ||
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(interrupts[INT_SEV])
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);
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}
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/**
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* This function is used to check if a wfi operation should sleep. If there
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* is an interrupt pending, even if it's masked, wfi doesn't sleep.
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* @return any interrupts pending
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*/
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bool
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checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const
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{
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uint64_t maskedIntStatus;
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bool virtWake;
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maskedIntStatus = intStatus & ~((1 << INT_VIRT_IRQ) |
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(1 << INT_VIRT_FIQ));
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virtWake = (hcr.vi || interrupts[INT_VIRT_IRQ]) && hcr.imo;
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virtWake |= (hcr.vf || interrupts[INT_VIRT_FIQ]) && hcr.fmo;
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virtWake |= hcr.va && hcr.amo;
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virtWake &= (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
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return maskedIntStatus || virtWake;
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}
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uint32_t
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getISR(HCR hcr, CPSR cpsr, SCR scr)
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{
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bool useHcrMux;
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CPSR isr = 0; // ARM ARM states ISR reg uses same bit possitions as CPSR
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useHcrMux = (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
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isr.i = (useHcrMux & hcr.imo) ? (interrupts[INT_VIRT_IRQ] || hcr.vi)
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: interrupts[INT_IRQ];
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isr.f = (useHcrMux & hcr.fmo) ? (interrupts[INT_VIRT_FIQ] || hcr.vf)
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: interrupts[INT_FIQ];
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isr.a = (useHcrMux & hcr.amo) ? hcr.va : interrupts[INT_ABT];
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return isr;
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}
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/**
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* Check the state of a particular interrupt, ignoring CPSR masks.
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*
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* This method is primarily used when running the target CPU in a
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* hardware VM (e.g., KVM) to check if interrupts should be
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* delivered upon guest entry.
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*
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* @param interrupt Interrupt type to check the state of.
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* @return true if the interrupt is asserted, false otherwise.
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*/
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bool
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checkRaw(InterruptTypes interrupt) const
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{
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if (interrupt >= NumInterruptTypes)
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panic("Interrupt number out of range.\n");
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return interrupts[interrupt];
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}
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Fault
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getInterrupt(ThreadContext *tc)
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{
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assert(checkInterrupts(tc));
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HCR hcr = tc->readMiscReg(MISCREG_HCR);
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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// Calculate a few temp vars so we can work out if there's a pending
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// virtual interrupt, and if its allowed to happen
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// ARM ARM Issue C section B1.9.9, B1.9.11, and B1.9.13
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bool isHypMode = cpsr.mode == MODE_HYP;
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bool isSecure = inSecureState(tc);
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bool allowVIrq = !cpsr.i && hcr.imo && !isSecure && !isHypMode;
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bool allowVFiq = !cpsr.f && hcr.fmo && !isSecure && !isHypMode;
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bool allowVAbort = !cpsr.a && hcr.amo && !isSecure && !isHypMode;
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bool take_irq = takeInt(tc, INT_IRQ);
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bool take_fiq = takeInt(tc, INT_FIQ);
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bool take_ea = takeInt(tc, INT_ABT);
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if (interrupts[INT_IRQ] && take_irq)
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return std::make_shared<Interrupt>();
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if ((interrupts[INT_VIRT_IRQ] || hcr.vi) && allowVIrq)
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return std::make_shared<VirtualInterrupt>();
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if (interrupts[INT_FIQ] && take_fiq)
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return std::make_shared<FastInterrupt>();
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if ((interrupts[INT_VIRT_FIQ] || hcr.vf) && allowVFiq)
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return std::make_shared<VirtualFastInterrupt>();
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if (interrupts[INT_ABT] && take_ea)
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return std::make_shared<SystemError>();
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if (hcr.va && allowVAbort)
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return std::make_shared<VirtualDataAbort>(
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0, TlbEntry::DomainType::NoAccess, false,
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ArmFault::AsynchronousExternalAbort);
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if (interrupts[INT_RST])
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return std::make_shared<Reset>();
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if (interrupts[INT_SEV])
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return std::make_shared<ArmSev>();
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panic("intStatus and interrupts not in sync\n");
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}
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void
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updateIntrInfo(ThreadContext *tc)
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{
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; // nothing to do
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}
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void
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serialize(CheckpointOut &cp) const
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{
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SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
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SERIALIZE_SCALAR(intStatus);
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}
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void
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unserialize(CheckpointIn &cp)
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{
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UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
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UNSERIALIZE_SCALAR(intStatus);
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}
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};
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} // namespace ARM_ISA
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#endif // __ARCH_ARM_INTERRUPT_HH__
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