141 lines
4.3 KiB
C++
141 lines
4.3 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ron Dreslinski
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* Andreas Hansson
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*/
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/**
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* @file
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* SimpleMemory declaration
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*/
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#ifndef __SIMPLE_MEMORY_HH__
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#define __SIMPLE_MEMORY_HH__
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#include "mem/abstract_mem.hh"
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#include "mem/tport.hh"
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#include "params/SimpleMemory.hh"
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/**
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* The simple memory is a basic single-ported memory controller with
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* an configurable throughput and latency, potentially with a variance
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* added to the latter. It uses a QueueSlavePort to avoid dealing with
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* the flow control of sending responses.
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* @sa \ref gem5MemorySystem "gem5 Memory System"
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*/
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class SimpleMemory : public AbstractMemory
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{
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private:
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class MemoryPort : public QueuedSlavePort
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{
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private:
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/// Queue holding the response packets
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SlavePacketQueue queueImpl;
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SimpleMemory& memory;
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public:
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MemoryPort(const std::string& _name, SimpleMemory& _memory);
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protected:
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Tick recvAtomic(PacketPtr pkt);
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void recvFunctional(PacketPtr pkt);
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bool recvTimingReq(PacketPtr pkt);
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AddrRangeList getAddrRanges() const;
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};
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MemoryPort port;
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Tick lat;
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Tick lat_var;
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/// Bandwidth in ticks per byte
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const double bandwidth;
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/**
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* Track the state of the memory as either idle or busy, no need
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* for an enum with only two states.
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*/
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bool isBusy;
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/**
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* Remember if we have to retry an outstanding request that
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* arrived while we were busy.
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*/
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bool retryReq;
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/**
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* Release the memory after being busy and send a retry if a
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* request was rejected in the meanwhile.
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*/
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void release();
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EventWrapper<SimpleMemory, &SimpleMemory::release> releaseEvent;
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public:
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SimpleMemory(const SimpleMemoryParams *p);
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virtual ~SimpleMemory() { }
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unsigned int drain(Event* de);
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virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
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virtual void init();
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protected:
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Tick doAtomicAccess(PacketPtr pkt);
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void doFunctionalAccess(PacketPtr pkt);
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bool recvTimingReq(PacketPtr pkt);
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Tick calculateLatency(PacketPtr pkt);
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};
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#endif //__SIMPLE_MEMORY_HH__
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