117 lines
3.8 KiB
C++
117 lines
3.8 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Ali Saidi
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*/
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#include <string>
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#include "arch/alpha/ev5.hh"
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#include "arch/alpha/vtophys.hh"
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#include "base/chunk_generator.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "mem/vport.hh"
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using namespace std;
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namespace AlphaISA {
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PageTableEntry
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kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr)
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{
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Addr level1_pte = ptbr + vaddr.level1();
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PageTableEntry level1 = mem->read<uint64_t>(level1_pte);
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if (!level1.valid()) {
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DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
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return 0;
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}
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Addr level2_pte = level1.paddr() + vaddr.level2();
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PageTableEntry level2 = mem->read<uint64_t>(level2_pte);
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if (!level2.valid()) {
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DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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Addr level3_pte = level2.paddr() + vaddr.level3();
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PageTableEntry level3 = mem->read<uint64_t>(level3_pte);
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if (!level3.valid()) {
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DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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return level3;
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}
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Addr
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vtophys(Addr vaddr)
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{
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Addr paddr = 0;
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if (IsUSeg(vaddr))
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DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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else if (IsK0Seg(vaddr))
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paddr = K0Seg2Phys(vaddr);
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else
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panic("vtophys: ptbr is not set on virtual lookup");
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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Addr
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vtophys(ThreadContext *tc, Addr addr)
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{
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VAddr vaddr = addr;
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Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20);
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Addr paddr = 0;
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//@todo Andrew couldn't remember why he commented some of this code
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//so I put it back in. Perhaps something to do with gdb debugging?
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if (PcPAL(vaddr) && (vaddr < PalMax)) {
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paddr = vaddr & ~ULL(1);
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} else {
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if (IsK0Seg(vaddr)) {
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paddr = K0Seg2Phys(vaddr);
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} else if (!ptbr) {
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paddr = vaddr;
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} else {
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PageTableEntry pte =
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kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
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if (pte.valid())
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paddr = pte.paddr() | vaddr.offset();
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}
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}
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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} // namespace AlphaISA
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