812 lines
33 KiB
C++
812 lines
33 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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header_output = ""
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decoder_output = ""
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exec_output = ""
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calcGECode = '''
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CondCodes = insertBits(CondCodes, 19, 16, resTemp);
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'''
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calcQCode = '''
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CondCodes = CondCodes | ((resTemp & 1) << 27);
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'''
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calcCcCode = '''
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uint16_t _ic, _iv, _iz, _in;
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_in = (resTemp >> %(negBit)d) & 1;
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_iz = (resTemp == 0);
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_iv = %(ivValue)s & 1;
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_ic = %(icValue)s & 1;
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CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
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(CondCodes & 0x0FFFFFFF);
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DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
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_in, _iz, _ic, _iv);
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'''
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# Dict of code to set the carry flag. (imm, reg, reg-reg)
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oldC = 'CondCodes<29:>'
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oldV = 'CondCodes<28:>'
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carryCode = {
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"none": (oldC, oldC, oldC),
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"llbit": (oldC, oldC, oldC),
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"saturate": ('0', '0', '0'),
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"overflow": ('0', '0', '0'),
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"ge": ('0', '0', '0'),
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"add": ('findCarry(32, resTemp, Op1, secondOp)',
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'findCarry(32, resTemp, Op1, secondOp)',
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'findCarry(32, resTemp, Op1, secondOp)'),
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"sub": ('findCarry(32, resTemp, Op1, ~secondOp)',
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'findCarry(32, resTemp, Op1, ~secondOp)',
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'findCarry(32, resTemp, Op1, ~secondOp)'),
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"rsb": ('findCarry(32, resTemp, secondOp, ~Op1)',
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'findCarry(32, resTemp, secondOp, ~Op1)',
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'findCarry(32, resTemp, secondOp, ~Op1)'),
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"logic": ('(rotC ? bits(secondOp, 31) : %s)' % oldC,
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'shift_carry_imm(Op2, shiftAmt, shiftType, %s)' % oldC,
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'shift_carry_rs(Op2, Shift<7:0>, shiftType, %s)' % oldC)
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}
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# Dict of code to set the overflow flag.
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overflowCode = {
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"none": oldV,
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"llbit": oldV,
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"saturate": '0',
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"overflow": '0',
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"ge": '0',
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"add": 'findOverflow(32, resTemp, Op1, secondOp)',
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"sub": 'findOverflow(32, resTemp, Op1, ~secondOp)',
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"rsb": 'findOverflow(32, resTemp, secondOp, ~Op1)',
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"logic": oldV
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}
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secondOpRe = re.compile("secondOp")
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immOp2 = "imm"
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regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)"
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regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)"
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def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
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buildCc = True, buildNonCc = True):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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if flagType == "llbit":
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negBit = 63
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if flagType == "saturate":
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immCcCode = calcQCode
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elif flagType == "ge":
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immCcCode = calcGECode
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else:
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immCcCode = calcCcCode % {
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"icValue": secondOpRe.sub(immOp2, cCode[0]),
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"ivValue": secondOpRe.sub(immOp2, vCode),
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"negBit": negBit
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}
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immCode = secondOpRe.sub(immOp2, code)
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immIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataImmOp",
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{"code" : immCode,
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"predicate_test": predicateTest})
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immIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
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"DataImmOp",
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{"code" : immCode + immCcCode,
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"predicate_test": predicateTest})
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def subst(iop):
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global header_output, decoder_output, exec_output
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header_output += DataImmDeclare.subst(iop)
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decoder_output += DataImmConstructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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if buildNonCc:
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subst(immIop)
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if buildCc:
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subst(immIopCc)
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def buildRegDataInst(mnem, code, flagType = "logic", suffix = "Reg", \
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buildCc = True, buildNonCc = True):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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if flagType == "llbit":
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negBit = 63
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if flagType == "saturate":
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regCcCode = calcQCode
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elif flagType == "ge":
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regCcCode = calcGECode
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else:
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regCcCode = calcCcCode % {
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"icValue": secondOpRe.sub(regOp2, cCode[1]),
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"ivValue": secondOpRe.sub(regOp2, vCode),
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"negBit": negBit
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}
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regCode = secondOpRe.sub(regOp2, code)
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regIop = InstObjParams(mnem, mnem.capitalize() + suffix, "DataRegOp",
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{"code" : regCode,
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"predicate_test": predicateTest})
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regIopCc = InstObjParams(mnem + "s", mnem.capitalize() + suffix + "Cc",
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"DataRegOp",
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{"code" : regCode + regCcCode,
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"predicate_test": predicateTest})
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def subst(iop):
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global header_output, decoder_output, exec_output
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header_output += DataRegDeclare.subst(iop)
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decoder_output += DataRegConstructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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if buildNonCc:
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subst(regIop)
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if buildCc:
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subst(regIopCc)
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def buildRegRegDataInst(mnem, code, flagType = "logic", \
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suffix = "RegReg", \
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buildCc = True, buildNonCc = True):
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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negBit = 31
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if flagType == "llbit":
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negBit = 63
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if flagType == "saturate":
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regRegCcCode = calcQCode
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elif flagType == "ge":
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regRegCcCode = calcGECode
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else:
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regRegCcCode = calcCcCode % {
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"icValue": secondOpRe.sub(regRegOp2, cCode[2]),
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"ivValue": secondOpRe.sub(regRegOp2, vCode),
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"negBit": negBit
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}
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regRegCode = secondOpRe.sub(regRegOp2, code)
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regRegIop = InstObjParams(mnem, mnem.capitalize() + suffix,
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"DataRegRegOp",
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{"code" : regRegCode,
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"predicate_test": predicateTest})
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regRegIopCc = InstObjParams(mnem + "s",
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mnem.capitalize() + suffix + "Cc",
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"DataRegRegOp",
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{"code" : regRegCode + regRegCcCode,
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"predicate_test": predicateTest})
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def subst(iop):
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global header_output, decoder_output, exec_output
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header_output += DataRegRegDeclare.subst(iop)
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decoder_output += DataRegRegConstructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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if buildNonCc:
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subst(regRegIop)
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if buildCc:
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subst(regRegIopCc)
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def buildDataInst(mnem, code, flagType = "logic", \
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aiw = True, regRegAiw = True,
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subsPcLr = True):
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regRegCode = instCode = code
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if aiw:
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instCode = "AIW" + instCode
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if regRegAiw:
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regRegCode = "AIW" + regRegCode
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buildImmDataInst(mnem, instCode, flagType)
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buildRegDataInst(mnem, instCode, flagType)
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buildRegRegDataInst(mnem, regRegCode, flagType)
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if subsPcLr:
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code += '''
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes, Spsr, 0xF, true);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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'''
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buildImmDataInst(mnem + 's', code, flagType,
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suffix = "ImmPclr", buildCc = False)
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buildRegDataInst(mnem + 's', code, flagType,
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suffix = "RegPclr", buildCc = False)
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buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
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buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
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buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
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buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
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buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
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buildImmDataInst("adr", '''
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Dest = resTemp = (readPC(xc) & ~0x3) +
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(op1 ? secondOp : -secondOp);
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''')
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buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
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buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
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buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
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buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
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buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
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buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
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buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
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buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
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buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
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buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
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buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
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buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
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buildDataInst("movt",
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"Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
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aiw = False)
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buildRegDataInst("qadd", '''
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int32_t midRes;
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resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw);
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Dest = midRes;
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''', flagType="saturate", buildNonCc=False)
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buildRegDataInst("qadd16", '''
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int32_t midRes;
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for (unsigned i = 0; i < 2; i++) {
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int high = (i + 1) * 16 - 1;
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int low = i * 16;
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int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
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int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
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saturateOp<16>(midRes, arg1, arg2);
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replaceBits(resTemp, high, low, midRes);
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}
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Dest = resTemp;
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''', flagType="none", buildCc=False)
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buildRegDataInst("qadd8", '''
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int32_t midRes;
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for (unsigned i = 0; i < 4; i++) {
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int high = (i + 1) * 8 - 1;
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int low = i * 8;
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int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
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int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
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saturateOp<8>(midRes, arg1, arg2);
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replaceBits(resTemp, high, low, midRes);
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}
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Dest = resTemp;
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''', flagType="none", buildCc=False)
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buildRegDataInst("qdadd", '''
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int32_t midRes;
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resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
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saturateOp<32>(midRes, Op1.sw, midRes);
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Dest = midRes;
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''', flagType="saturate", buildNonCc=False)
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buildRegDataInst("qsub", '''
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int32_t midRes;
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resTemp = saturateOp<32>(midRes, Op1.sw, Op2.sw, true);
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Dest = midRes;
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''', flagType="saturate")
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buildRegDataInst("qsub16", '''
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int32_t midRes;
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for (unsigned i = 0; i < 2; i++) {
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int high = (i + 1) * 16 - 1;
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int low = i * 16;
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int64_t arg1 = sext<16>(bits(Op1.sw, high, low));
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int64_t arg2 = sext<16>(bits(Op2.sw, high, low));
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saturateOp<16>(midRes, arg1, arg2, true);
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replaceBits(resTemp, high, low, midRes);
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}
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Dest = resTemp;
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''', flagType="none", buildCc=False)
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buildRegDataInst("qsub8", '''
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int32_t midRes;
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for (unsigned i = 0; i < 4; i++) {
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int high = (i + 1) * 8 - 1;
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int low = i * 8;
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int64_t arg1 = sext<8>(bits(Op1.sw, high, low));
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int64_t arg2 = sext<8>(bits(Op2.sw, high, low));
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saturateOp<8>(midRes, arg1, arg2, true);
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replaceBits(resTemp, high, low, midRes);
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}
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Dest = resTemp;
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''', flagType="none", buildCc=False)
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buildRegDataInst("qdsub", '''
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int32_t midRes;
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resTemp = saturateOp<32>(midRes, Op2.sw, Op2.sw) |
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saturateOp<32>(midRes, Op1.sw, midRes, true);
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Dest = midRes;
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''', flagType="saturate", buildNonCc=False)
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buildRegDataInst("qasx", '''
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int32_t midRes;
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int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
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int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
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int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
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int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
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saturateOp<16>(midRes, arg1Low, arg2High, true);
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replaceBits(resTemp, 15, 0, midRes);
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saturateOp<16>(midRes, arg1High, arg2Low);
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replaceBits(resTemp, 31, 16, midRes);
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Dest = resTemp;
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''', flagType="none", buildCc=False)
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buildRegDataInst("qsax", '''
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int32_t midRes;
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int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
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int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
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int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
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int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
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saturateOp<16>(midRes, arg1Low, arg2High);
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replaceBits(resTemp, 15, 0, midRes);
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saturateOp<16>(midRes, arg1High, arg2Low, true);
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replaceBits(resTemp, 31, 16, midRes);
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Dest = resTemp;
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''', flagType="none", buildCc=False)
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buildRegDataInst("sadd8", '''
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uint32_t geBits = 0;
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resTemp = 0;
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for (unsigned i = 0; i < 4; i++) {
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int high = (i + 1) * 8 - 1;
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int low = i * 8;
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int32_t midRes = sext<8>(bits(Op1.sw, high, low)) +
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sext<8>(bits(Op2.sw, high, low));
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replaceBits(resTemp, high, low, midRes);
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if (midRes >= 0) {
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geBits = geBits | (1 << i);
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}
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}
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Dest = resTemp;
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resTemp = geBits;
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''', flagType="ge", buildNonCc=False)
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buildRegDataInst("sadd16", '''
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uint32_t geBits = 0;
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resTemp = 0;
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for (unsigned i = 0; i < 2; i++) {
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int high = (i + 1) * 16 - 1;
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int low = i * 16;
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int32_t midRes = sext<16>(bits(Op1.sw, high, low)) +
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sext<16>(bits(Op2.sw, high, low));
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replaceBits(resTemp, high, low, midRes);
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if (midRes >= 0) {
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geBits = geBits | (0x3 << (i * 2));
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}
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}
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Dest = resTemp;
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resTemp = geBits;
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''', flagType="ge", buildNonCc=False)
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buildRegDataInst("ssub8", '''
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uint32_t geBits = 0;
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resTemp = 0;
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for (unsigned i = 0; i < 4; i++) {
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int high = (i + 1) * 8 - 1;
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int low = i * 8;
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int32_t midRes = sext<8>(bits(Op1.sw, high, low)) -
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sext<8>(bits(Op2.sw, high, low));
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replaceBits(resTemp, high, low, midRes);
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if (midRes >= 0) {
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geBits = geBits | (1 << i);
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}
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}
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Dest = resTemp;
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resTemp = geBits;
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''', flagType="ge", buildNonCc=False)
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buildRegDataInst("ssub16", '''
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uint32_t geBits = 0;
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resTemp = 0;
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for (unsigned i = 0; i < 2; i++) {
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int high = (i + 1) * 16 - 1;
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int low = i * 16;
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int32_t midRes = sext<16>(bits(Op1.sw, high, low)) -
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sext<16>(bits(Op2.sw, high, low));
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replaceBits(resTemp, high, low, midRes);
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if (midRes >= 0) {
|
|
geBits = geBits | (0x3 << (i * 2));
|
|
}
|
|
}
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=False)
|
|
buildRegDataInst("sasx", '''
|
|
int32_t midRes, geBits = 0;
|
|
resTemp = 0;
|
|
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
|
|
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
|
|
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
|
|
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
|
|
midRes = arg1Low - arg2High;
|
|
if (midRes >= 0) {
|
|
geBits = geBits | 0x3;
|
|
}
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = arg1High + arg2Low;
|
|
if (midRes >= 0) {
|
|
geBits = geBits | 0xc;
|
|
}
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=True)
|
|
buildRegDataInst("ssax", '''
|
|
int32_t midRes, geBits = 0;
|
|
resTemp = 0;
|
|
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
|
|
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
|
|
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
|
|
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
|
|
midRes = arg1Low + arg2High;
|
|
if (midRes >= 0) {
|
|
geBits = geBits | 0x3;
|
|
}
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = arg1High - arg2Low;
|
|
if (midRes >= 0) {
|
|
geBits = geBits | 0xc;
|
|
}
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=True)
|
|
|
|
buildRegDataInst("shadd8", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
int32_t midRes =
|
|
(uint64_t)(sext<8>(bits(Op1.sw, high, low)) +
|
|
sext<8>(bits(Op2.sw, high, low))) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("shadd16", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
int32_t midRes =
|
|
(uint64_t)(sext<16>(bits(Op1.sw, high, low)) +
|
|
sext<16>(bits(Op2.sw, high, low))) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("shsub8", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
int32_t midRes =
|
|
(uint64_t)(sext<8>(bits(Op1.sw, high, low)) -
|
|
sext<8>(bits(Op2.sw, high, low))) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("shsub16", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
int32_t midRes =
|
|
(uint64_t)(sext<16>(bits(Op1.sw, high, low)) -
|
|
sext<16>(bits(Op2.sw, high, low))) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("shasx", '''
|
|
int32_t midRes;
|
|
resTemp = 0;
|
|
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
|
|
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
|
|
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
|
|
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
|
|
midRes = (uint64_t)(arg1Low - arg2High) >> 1;
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = (arg1High + arg2Low) >> 1;
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=True)
|
|
buildRegDataInst("shsax", '''
|
|
int32_t midRes;
|
|
resTemp = 0;
|
|
int64_t arg1Low = sext<16>(bits(Op1.sw, 15, 0));
|
|
int64_t arg1High = sext<16>(bits(Op1.sw, 31, 16));
|
|
int64_t arg2Low = sext<16>(bits(Op2.sw, 15, 0));
|
|
int64_t arg2High = sext<16>(bits(Op2.sw, 31, 16));
|
|
midRes = (uint64_t)(arg1Low + arg2High) >> 1;
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = (uint64_t)(arg1High - arg2Low) >> 1;
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=True)
|
|
|
|
buildRegDataInst("uqadd16", '''
|
|
uint32_t midRes;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
uint64_t arg1 = bits(Op1, high, low);
|
|
uint64_t arg2 = bits(Op2, high, low);
|
|
uSaturateOp<16>(midRes, arg1, arg2);
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uqadd8", '''
|
|
uint32_t midRes;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
uint64_t arg1 = bits(Op1, high, low);
|
|
uint64_t arg2 = bits(Op2, high, low);
|
|
uSaturateOp<8>(midRes, arg1, arg2);
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uqsub16", '''
|
|
uint32_t midRes;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
uint64_t arg1 = bits(Op1, high, low);
|
|
uint64_t arg2 = bits(Op2, high, low);
|
|
uSaturateOp<16>(midRes, arg1, arg2, true);
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uqsub8", '''
|
|
uint32_t midRes;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
uint64_t arg1 = bits(Op1, high, low);
|
|
uint64_t arg2 = bits(Op2, high, low);
|
|
uSaturateOp<8>(midRes, arg1, arg2, true);
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uqasx", '''
|
|
uint32_t midRes;
|
|
uint64_t arg1Low = bits(Op1.sw, 15, 0);
|
|
uint64_t arg1High = bits(Op1.sw, 31, 16);
|
|
uint64_t arg2Low = bits(Op2.sw, 15, 0);
|
|
uint64_t arg2High = bits(Op2.sw, 31, 16);
|
|
uSaturateOp<16>(midRes, arg1Low, arg2High, true);
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
uSaturateOp<16>(midRes, arg1High, arg2Low);
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uqsax", '''
|
|
uint32_t midRes;
|
|
uint64_t arg1Low = bits(Op1.sw, 15, 0);
|
|
uint64_t arg1High = bits(Op1.sw, 31, 16);
|
|
uint64_t arg2Low = bits(Op2.sw, 15, 0);
|
|
uint64_t arg2High = bits(Op2.sw, 31, 16);
|
|
uSaturateOp<16>(midRes, arg1Low, arg2High);
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
uSaturateOp<16>(midRes, arg1High, arg2Low, true);
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
|
|
buildRegDataInst("uadd16", '''
|
|
uint32_t geBits = 0;
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
int32_t midRes = bits(Op1, high, low) +
|
|
bits(Op2, high, low);
|
|
if (midRes >= 0x10000) {
|
|
geBits = geBits | (0x3 << (i * 2));
|
|
}
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=False)
|
|
buildRegDataInst("uadd8", '''
|
|
uint32_t geBits = 0;
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
int32_t midRes = bits(Op1, high, low) +
|
|
bits(Op2, high, low);
|
|
if (midRes >= 0x100) {
|
|
geBits = geBits | (1 << i);
|
|
}
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=False)
|
|
buildRegDataInst("usub16", '''
|
|
uint32_t geBits = 0;
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
int32_t midRes = bits(Op1, high, low) -
|
|
bits(Op2, high, low);
|
|
if (midRes >= 0) {
|
|
geBits = geBits | (0x3 << (i * 2));
|
|
}
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=False)
|
|
buildRegDataInst("usub8", '''
|
|
uint32_t geBits = 0;
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
int32_t midRes = bits(Op1, high, low) -
|
|
bits(Op2, high, low);
|
|
if (midRes >= 0) {
|
|
geBits = geBits | (1 << i);
|
|
}
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=False)
|
|
buildRegDataInst("uasx", '''
|
|
int32_t midRes, geBits = 0;
|
|
resTemp = 0;
|
|
int64_t arg1Low = bits(Op1.sw, 15, 0);
|
|
int64_t arg1High = bits(Op1.sw, 31, 16);
|
|
int64_t arg2Low = bits(Op2.sw, 15, 0);
|
|
int64_t arg2High = bits(Op2.sw, 31, 16);
|
|
midRes = arg1Low - arg2High;
|
|
if (midRes >= 0) {
|
|
geBits = geBits | 0x3;
|
|
}
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = arg1High + arg2Low;
|
|
if (midRes >= 0x10000) {
|
|
geBits = geBits | 0xc;
|
|
}
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=False)
|
|
buildRegDataInst("usax", '''
|
|
int32_t midRes, geBits = 0;
|
|
resTemp = 0;
|
|
int64_t arg1Low = bits(Op1.sw, 15, 0);
|
|
int64_t arg1High = bits(Op1.sw, 31, 16);
|
|
int64_t arg2Low = bits(Op2.sw, 15, 0);
|
|
int64_t arg2High = bits(Op2.sw, 31, 16);
|
|
midRes = arg1Low + arg2High;
|
|
if (midRes >= 0x10000) {
|
|
geBits = geBits | 0x3;
|
|
}
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = arg1High - arg2Low;
|
|
if (midRes >= 0) {
|
|
geBits = geBits | 0xc;
|
|
}
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
resTemp = geBits;
|
|
''', flagType="ge", buildNonCc=False)
|
|
|
|
buildRegDataInst("uhadd16", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
int32_t midRes = (bits(Op1, high, low) +
|
|
bits(Op2, high, low)) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uhadd8", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
int32_t midRes = (bits(Op1, high, low) +
|
|
bits(Op2, high, low)) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uhsub16", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 2; i++) {
|
|
int high = (i + 1) * 16 - 1;
|
|
int low = i * 16;
|
|
int32_t midRes = (bits(Op1, high, low) -
|
|
bits(Op2, high, low)) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uhsub8", '''
|
|
resTemp = 0;
|
|
for (unsigned i = 0; i < 4; i++) {
|
|
int high = (i + 1) * 8 - 1;
|
|
int low = i * 8;
|
|
int32_t midRes = (bits(Op1, high, low) -
|
|
bits(Op2, high, low)) >> 1;
|
|
replaceBits(resTemp, high, low, midRes);
|
|
}
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uhasx", '''
|
|
int32_t midRes;
|
|
resTemp = 0;
|
|
int64_t arg1Low = bits(Op1.sw, 15, 0);
|
|
int64_t arg1High = bits(Op1.sw, 31, 16);
|
|
int64_t arg2Low = bits(Op2.sw, 15, 0);
|
|
int64_t arg2High = bits(Op2.sw, 31, 16);
|
|
midRes = (arg1Low - arg2High) >> 1;
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = (arg1High + arg2Low) >> 1;
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("uhsax", '''
|
|
int32_t midRes;
|
|
resTemp = 0;
|
|
int64_t arg1Low = bits(Op1.sw, 15, 0);
|
|
int64_t arg1High = bits(Op1.sw, 31, 16);
|
|
int64_t arg2Low = bits(Op2.sw, 15, 0);
|
|
int64_t arg2High = bits(Op2.sw, 31, 16);
|
|
midRes = (arg1Low + arg2High) >> 1;
|
|
replaceBits(resTemp, 15, 0, midRes);
|
|
midRes = (arg1High - arg2Low) >> 1;
|
|
replaceBits(resTemp, 31, 16, midRes);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
|
|
buildRegDataInst("pkhbt", '''
|
|
uint32_t resTemp = 0;
|
|
uint16_t arg1Low = bits(Op1, 15, 0);
|
|
uint16_t arg2High = bits(secondOp, 31, 16);
|
|
replaceBits(resTemp, 15, 0, arg1Low);
|
|
replaceBits(resTemp, 31, 16, arg2High);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
buildRegDataInst("pkhtb", '''
|
|
uint32_t resTemp = 0;
|
|
uint16_t arg1High = bits(Op1, 31, 16);
|
|
uint16_t arg2Low = bits(secondOp, 15, 0);
|
|
replaceBits(resTemp, 15, 0, arg2Low);
|
|
replaceBits(resTemp, 31, 16, arg1High);
|
|
Dest = resTemp;
|
|
''', flagType="none", buildCc=False)
|
|
}};
|