88e22ee081
Key was adding support for cloning port references (trickier than it sounds).
Got rid of class/instance thing and go back to instance cloning...
still don't allow changing SimObject parameters/children after a
class (instance) has been subclassed or instantiated (or cloned), which
should avoid bizarre unintended behavior.
configs/test/fs.py:
Add ".port" to busses to get a port reference.
Get rid of commented-out code.
src/python/m5/__init__.py:
resolveSimObject should call getCCObject() instead of createCCObject()
to avoid cycles in recursively creating objects.
src/python/m5/config.py:
Get rid of class/instance thing and go back to instance cloning.
Deep copy has to happen only on instance cloning then (and not on subclassing).
Add getCCObject() method to force creation of C++ SimObject without
recursively creating its children.
Add support for cloning port references (trickier than it sounds).
Also clean up some very obsolete comments.
src/python/m5/objects/Bridge.py:
src/python/m5/objects/Device.py:
Add ports.
--HG--
extra : convert_revision : 4816d05ead0de520748aace06dbd1911a33f0af8
225 lines
7.1 KiB
Python
225 lines
7.1 KiB
Python
import m5
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from m5.objects import *
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import os
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from SysPaths import *
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parser = optparse.OptionParser(option_list=m5.standardOptions)
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parser.add_option("-t", "--timing", action="store_true")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# Base for tests is directory containing this file.
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test_base = os.path.dirname(__file__)
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linux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
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class IdeControllerPciData(PciConfigData):
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VendorID = 0x8086
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DeviceID = 0x7111
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Command = 0x0
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Status = 0x280
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Revision = 0x0
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ClassCode = 0x01
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SubClassCode = 0x01
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ProgIF = 0x85
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BAR0 = 0x00000001
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BAR1 = 0x00000001
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BAR2 = 0x00000001
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BAR3 = 0x00000001
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BAR4 = 0x00000001
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BAR5 = 0x00000001
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InterruptLine = 0x1f
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InterruptPin = 0x01
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BAR0Size = '8B'
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BAR1Size = '4B'
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BAR2Size = '8B'
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BAR3Size = '4B'
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BAR4Size = '16B'
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class SinicPciData(PciConfigData):
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VendorID = 0x1291
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DeviceID = 0x1293
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '64kB'
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class NSGigEPciData(PciConfigData):
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VendorID = 0x100B
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DeviceID = 0x0022
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000001
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '256B'
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BAR1Size = '4kB'
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class LinuxRootDisk(IdeDisk):
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raw_image = RawDiskImage(image_file=linux_image, read_only=True)
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image = CowDiskImage(child=Parent.raw_image, read_only=False)
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class LinuxSwapDisk(IdeDisk):
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raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'),
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read_only=True)
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image = CowDiskImage(child = Parent.raw_image, read_only=False)
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class SpecwebFilesetDisk(IdeDisk):
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raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'),
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read_only=True)
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image = CowDiskImage(child = Parent.raw_image, read_only=False)
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class BaseTsunami(Tsunami):
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cchip = TsunamiCChip(pio_addr=0x801a0000000)
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pchip = TsunamiPChip(pio_addr=0x80180000000)
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pciconfig = PciConfigAll(pio_addr=0x801fe000000)
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fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
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fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
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fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
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fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
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fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
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fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
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fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
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fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
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fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
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fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
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fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
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fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
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fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
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fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
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fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
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fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
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fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
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fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
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fake_ata1 = IsaFake(pio_addr=0x801fc000170)
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fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
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io = TsunamiIO(pio_addr=0x801fc000000)
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uart = Uart8250(pio_addr=0x801fc0003f8)
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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etherint = NSGigEInt(device=Parent.ethernet)
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console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
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class LinuxTsunami(BaseTsunami):
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disk0 = LinuxRootDisk(driveID='master')
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disk1 = SpecwebFilesetDisk(driveID='slave')
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disk2 = LinuxSwapDisk(driveID='master')
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ide = IdeController(disks=[Parent.disk0, Parent.disk1, Parent.disk2],
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configdata=IdeControllerPciData(),
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pci_func=0, pci_dev=0, pci_bus=0)
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class MyLinuxAlphaSystem(LinuxAlphaSystem):
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magicbus = Bus(bus_id=0)
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magicbus2 = Bus(bus_id=1)
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bridge = Bridge()
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physmem = PhysicalMemory(range = AddrRange('128MB'))
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bridge.side_a = magicbus.port
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bridge.side_b = magicbus2.port
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physmem.port = magicbus2.port
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tsunami = LinuxTsunami()
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tsunami.cchip.pio = magicbus.port
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tsunami.pchip.pio = magicbus.port
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tsunami.pciconfig.pio = magicbus.port
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tsunami.fake_sm_chip.pio = magicbus.port
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tsunami.ethernet.pio = magicbus.port
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tsunami.ethernet.dma = magicbus.port
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tsunami.fake_uart1.pio = magicbus.port
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tsunami.fake_uart2.pio = magicbus.port
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tsunami.fake_uart3.pio = magicbus.port
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tsunami.fake_uart4.pio = magicbus.port
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tsunami.ide.pio = magicbus.port
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tsunami.ide.dma = magicbus.port
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tsunami.fake_ppc.pio = magicbus.port
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tsunami.fake_OROM.pio = magicbus.port
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tsunami.fake_pnp_addr.pio = magicbus.port
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tsunami.fake_pnp_write.pio = magicbus.port
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tsunami.fake_pnp_read0.pio = magicbus.port
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tsunami.fake_pnp_read1.pio = magicbus.port
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tsunami.fake_pnp_read2.pio = magicbus.port
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tsunami.fake_pnp_read3.pio = magicbus.port
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tsunami.fake_pnp_read4.pio = magicbus.port
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tsunami.fake_pnp_read5.pio = magicbus.port
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tsunami.fake_pnp_read6.pio = magicbus.port
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tsunami.fake_pnp_read7.pio = magicbus.port
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tsunami.fake_ata0.pio = magicbus.port
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tsunami.fake_ata1.pio = magicbus.port
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tsunami.fb.pio = magicbus.port
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tsunami.io.pio = magicbus.port
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tsunami.uart.pio = magicbus.port
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tsunami.console.pio = magicbus.port
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raw_image = RawDiskImage(image_file=disk('linux-latest.img'),
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read_only=True)
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simple_disk = SimpleDisk(disk=Parent.raw_image)
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intrctrl = IntrControl()
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if options.timing:
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cpu = TimingSimpleCPU()
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else:
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cpu = AtomicSimpleCPU()
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cpu.mem = magicbus2
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cpu.itb = AlphaITB()
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cpu.dtb = AlphaDTB()
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sim_console = SimConsole(listener=ConsoleListener(port=3456))
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kernel = binary('vmlinux')
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pal = binary('ts_osfpal')
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console = binary('console')
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boot_osflags = 'root=/dev/hda1 console=ttyS0'
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# readfile = os.path.join(test_base, 'halt.sh')
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class TsunamiRoot(System):
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pass
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def DualRoot(clientSystem, serverSystem):
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self = Root()
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self.client = clientSystem
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self.server = serverSystem
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self.etherdump = EtherDump(file='ethertrace')
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self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
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int2 = Parent.server.tsunami.etherint[0],
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dump = Parent.etherdump)
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self.clock = '5GHz'
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return self
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root = DualRoot(
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MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
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MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
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m5.instantiate(root)
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exit_event = m5.simulate()
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print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause()
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