gem5/tests/configs/inorder-timing.py
Andreas Hansson 3bc4ecdcb4 mem: More descriptive DRAM config names
This patch changes the class names of the variuos DRAM configurations
to better reflect what memory they are based on. The speed and
interface width is now part of the name, and also the alias that is
used to select them on the command line.

Some minor changes are done to the actual parameters, to better
reflect the named configurations. As a result of these changes the
regressions change slightly and the stats will be bumped in a separate
patch.
2013-05-30 12:54:14 -04:00

51 lines
2.2 KiB
Python

# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Steve Reinhardt
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
from Caches import *
cpu = InOrderCPU(cpu_id=0)
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
L1Cache(size = '256kB'),
L2Cache(size = '2MB'))
cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system)