dc8018a5c3
Result of running 'hg m5style --skip-all --fix-white -a'.
635 lines
19 KiB
C++
635 lines
19 KiB
C++
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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* Andrew Schultz
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*/
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#include "arch/alpha/tlb.hh"
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#include <algorithm>
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#include <memory>
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#include <string>
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#include <vector>
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#include "arch/alpha/faults.hh"
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#include "arch/alpha/pagetable.hh"
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#include "arch/generic/debugfaults.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/thread_context.hh"
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#include "debug/TLB.hh"
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#include "sim/full_system.hh"
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using namespace std;
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namespace AlphaISA {
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha TLB
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//
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#ifdef DEBUG
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bool uncacheBit39 = false;
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bool uncacheBit40 = false;
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#endif
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#define MODE2MASK(X) (1 << (X))
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TLB::TLB(const Params *p)
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: BaseTLB(p), table(p->size), nlu(0)
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{
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flushCache();
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}
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TLB::~TLB()
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{
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}
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void
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TLB::regStats()
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{
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fetch_hits
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.name(name() + ".fetch_hits")
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.desc("ITB hits");
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fetch_misses
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.name(name() + ".fetch_misses")
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.desc("ITB misses");
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fetch_acv
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.name(name() + ".fetch_acv")
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.desc("ITB acv");
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fetch_accesses
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.name(name() + ".fetch_accesses")
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.desc("ITB accesses");
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fetch_accesses = fetch_hits + fetch_misses;
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read_hits
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.name(name() + ".read_hits")
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.desc("DTB read hits")
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;
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read_misses
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.name(name() + ".read_misses")
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.desc("DTB read misses")
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;
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read_acv
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.name(name() + ".read_acv")
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.desc("DTB read access violations")
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;
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read_accesses
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.name(name() + ".read_accesses")
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.desc("DTB read accesses")
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;
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write_hits
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.name(name() + ".write_hits")
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.desc("DTB write hits")
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;
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write_misses
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.name(name() + ".write_misses")
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.desc("DTB write misses")
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;
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write_acv
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.name(name() + ".write_acv")
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.desc("DTB write access violations")
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;
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write_accesses
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.name(name() + ".write_accesses")
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.desc("DTB write accesses")
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;
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data_hits
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.name(name() + ".data_hits")
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.desc("DTB hits")
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;
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data_misses
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.name(name() + ".data_misses")
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.desc("DTB misses")
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;
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data_acv
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.name(name() + ".data_acv")
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.desc("DTB access violations")
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;
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data_accesses
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.name(name() + ".data_accesses")
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.desc("DTB accesses")
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;
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data_hits = read_hits + write_hits;
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data_misses = read_misses + write_misses;
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data_acv = read_acv + write_acv;
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data_accesses = read_accesses + write_accesses;
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}
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// look up an entry in the TLB
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TlbEntry *
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TLB::lookup(Addr vpn, uint8_t asn)
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{
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// assume not found...
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TlbEntry *retval = NULL;
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if (EntryCache[0]) {
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if (vpn == EntryCache[0]->tag &&
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(EntryCache[0]->asma || EntryCache[0]->asn == asn))
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retval = EntryCache[0];
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else if (EntryCache[1]) {
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if (vpn == EntryCache[1]->tag &&
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(EntryCache[1]->asma || EntryCache[1]->asn == asn))
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retval = EntryCache[1];
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else if (EntryCache[2] && vpn == EntryCache[2]->tag &&
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(EntryCache[2]->asma || EntryCache[2]->asn == asn))
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retval = EntryCache[2];
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}
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}
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if (retval == NULL) {
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i != lookupTable.end()) {
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while (i->first == vpn) {
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int index = i->second;
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TlbEntry *entry = &table[index];
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assert(entry->valid);
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if (vpn == entry->tag && (entry->asma || entry->asn == asn)) {
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retval = updateCache(entry);
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break;
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}
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++i;
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}
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}
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}
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DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
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retval ? "hit" : "miss", retval ? retval->ppn : 0);
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return retval;
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}
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Fault
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TLB::checkCacheability(RequestPtr &req, bool itb)
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{
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// in Alpha, cacheability is controlled by upper-level bits of the
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// physical address
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/*
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* We support having the uncacheable bit in either bit 39 or bit
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* 40. The Turbolaser platform (and EV5) support having the bit
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* in 39, but Tsunami (which Linux assumes uses an EV6) generates
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* accesses with the bit in 40. So we must check for both, but we
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* have debug flags to catch a weird case where both are used,
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* which shouldn't happen.
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*/
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if (req->getPaddr() & PAddrUncachedBit43) {
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// IPR memory space not implemented
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if (PAddrIprSpace(req->getPaddr())) {
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return std::make_shared<UnimpFault>(
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"IPR memory space not implemented!");
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} else {
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// mark request as uncacheable
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req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
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// Clear bits 42:35 of the physical address (10-2 in
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// Tsunami manual)
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req->setPaddr(req->getPaddr() & PAddrUncachedMask);
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}
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// We shouldn't be able to read from an uncachable address in Alpha as
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// we don't have a ROM and we don't want to try to fetch from a device
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// register as we destroy any data that is clear-on-read.
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if (req->isUncacheable() && itb)
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return std::make_shared<UnimpFault>(
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"CPU trying to fetch from uncached I/O");
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}
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return NoFault;
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}
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// insert a new TLB entry
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void
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TLB::insert(Addr addr, TlbEntry &entry)
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{
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flushCache();
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VAddr vaddr = addr;
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if (table[nlu].valid) {
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Addr oldvpn = table[nlu].tag;
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PageTable::iterator i = lookupTable.find(oldvpn);
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if (i == lookupTable.end())
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panic("TLB entry not found in lookupTable");
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int index;
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while ((index = i->second) != nlu) {
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if (table[index].tag != oldvpn)
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panic("TLB entry not found in lookupTable");
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++i;
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}
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DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
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lookupTable.erase(i);
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}
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DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn);
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table[nlu] = entry;
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table[nlu].tag = vaddr.vpn();
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table[nlu].valid = true;
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lookupTable.insert(make_pair(vaddr.vpn(), nlu));
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nextnlu();
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}
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void
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TLB::flushAll()
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{
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DPRINTF(TLB, "flushAll\n");
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std::fill(table.begin(), table.end(), TlbEntry());
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flushCache();
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lookupTable.clear();
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nlu = 0;
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}
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void
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TLB::flushProcesses()
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{
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flushCache();
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PageTable::iterator i = lookupTable.begin();
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PageTable::iterator end = lookupTable.end();
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while (i != end) {
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int index = i->second;
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TlbEntry *entry = &table[index];
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assert(entry->valid);
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// we can't increment i after we erase it, so save a copy and
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// increment it to get the next entry now
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PageTable::iterator cur = i;
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++i;
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if (!entry->asma) {
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DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index,
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entry->tag, entry->ppn);
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entry->valid = false;
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lookupTable.erase(cur);
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}
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}
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}
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void
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TLB::flushAddr(Addr addr, uint8_t asn)
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{
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flushCache();
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VAddr vaddr = addr;
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PageTable::iterator i = lookupTable.find(vaddr.vpn());
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if (i == lookupTable.end())
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return;
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while (i != lookupTable.end() && i->first == vaddr.vpn()) {
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int index = i->second;
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TlbEntry *entry = &table[index];
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assert(entry->valid);
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if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) {
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DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
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entry->ppn);
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// invalidate this entry
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entry->valid = false;
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lookupTable.erase(i++);
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} else {
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++i;
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}
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}
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}
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void
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TLB::serialize(CheckpointOut &cp) const
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{
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const unsigned size(table.size());
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SERIALIZE_SCALAR(size);
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SERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++)
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table[i].serializeSection(cp, csprintf("Entry%d", i));
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}
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void
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TLB::unserialize(CheckpointIn &cp)
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{
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unsigned size(0);
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UNSERIALIZE_SCALAR(size);
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UNSERIALIZE_SCALAR(nlu);
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table.resize(size);
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for (int i = 0; i < size; i++) {
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table[i].unserializeSection(cp, csprintf("Entry%d", i));
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if (table[i].valid) {
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lookupTable.insert(make_pair(table[i].tag, i));
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}
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}
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}
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Fault
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TLB::translateInst(RequestPtr req, ThreadContext *tc)
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{
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//If this is a pal pc, then set PHYSICAL
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if (FullSystem && PcPAL(req->getPC()))
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req->setFlags(Request::PHYSICAL);
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if (PcPAL(req->getPC())) {
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// strip off PAL PC marker (lsb is 1)
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req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
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fetch_hits++;
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return NoFault;
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}
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if (req->getFlags() & Request::PHYSICAL) {
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req->setPaddr(req->getVaddr());
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} else {
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// verify that this is a good virtual address
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if (!validVirtualAddress(req->getVaddr())) {
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fetch_acv++;
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return std::make_shared<ItbAcvFault>(req->getVaddr());
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}
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
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// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
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if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
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// only valid in kernel mode
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if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
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mode_kernel) {
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fetch_acv++;
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return std::make_shared<ItbAcvFault>(req->getVaddr());
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}
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req->setPaddr(req->getVaddr() & PAddrImplMask);
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// sign extend the physical address properly
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if (req->getPaddr() & PAddrUncachedBit40)
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req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
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else
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req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
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} else {
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// not a physical address: need to look up pte
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int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
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TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
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asn);
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if (!entry) {
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fetch_misses++;
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return std::make_shared<ItbPageFault>(req->getVaddr());
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}
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req->setPaddr((entry->ppn << PageShift) +
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(VAddr(req->getVaddr()).offset()
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& ~3));
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// check permissions for this access
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if (!(entry->xre &
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(1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
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// instruction access fault
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fetch_acv++;
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return std::make_shared<ItbAcvFault>(req->getVaddr());
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}
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fetch_hits++;
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}
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}
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// check that the physical address is ok (catch bad physical addresses)
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if (req->getPaddr() & ~PAddrImplMask) {
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return std::make_shared<MachineCheckFault>();
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}
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return checkCacheability(req, true);
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}
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Fault
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TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
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{
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mode_type mode =
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(mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
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/**
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* Check for alignment faults
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*/
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if (req->getVaddr() & (req->getSize() - 1)) {
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DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
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req->getSize());
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uint64_t flags = write ? MM_STAT_WR_MASK : 0;
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return std::make_shared<DtbAlignmentFault>(req->getVaddr(),
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req->getFlags(),
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flags);
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}
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if (PcPAL(req->getPC())) {
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mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ?
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(mode_type)ALT_MODE_AM(
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tc->readMiscRegNoEffect(IPR_ALT_MODE))
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: mode_kernel;
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}
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if (req->getFlags() & Request::PHYSICAL) {
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req->setPaddr(req->getVaddr());
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} else {
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// verify that this is a good virtual address
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if (!validVirtualAddress(req->getVaddr())) {
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if (write) { write_acv++; } else { read_acv++; }
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uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
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MM_STAT_BAD_VA_MASK |
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MM_STAT_ACV_MASK;
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return std::make_shared<DtbPageFault>(req->getVaddr(),
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req->getFlags(),
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flags);
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}
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// Check for "superpage" mapping
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if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
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// only valid in kernel mode
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if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
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mode_kernel) {
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if (write) { write_acv++; } else { read_acv++; }
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uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
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MM_STAT_ACV_MASK);
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return std::make_shared<DtbAcvFault>(req->getVaddr(),
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req->getFlags(),
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flags);
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}
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req->setPaddr(req->getVaddr() & PAddrImplMask);
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// sign extend the physical address properly
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if (req->getPaddr() & PAddrUncachedBit40)
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req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
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else
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req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
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} else {
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if (write)
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write_accesses++;
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else
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read_accesses++;
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int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
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// not a physical address: need to look up pte
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TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
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if (!entry) {
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// page fault
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if (write) { write_misses++; } else { read_misses++; }
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uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
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MM_STAT_DTB_MISS_MASK;
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return (req->getFlags() & AlphaRequestFlags::VPTE) ?
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(Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
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req->getFlags(),
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flags)) :
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(Fault)(std::make_shared<NDtbMissFault>(req->getVaddr(),
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req->getFlags(),
|
|
flags));
|
|
}
|
|
|
|
req->setPaddr((entry->ppn << PageShift) +
|
|
VAddr(req->getVaddr()).offset());
|
|
|
|
if (write) {
|
|
if (!(entry->xwe & MODE2MASK(mode))) {
|
|
// declare the instruction access fault
|
|
write_acv++;
|
|
uint64_t flags = MM_STAT_WR_MASK |
|
|
MM_STAT_ACV_MASK |
|
|
(entry->fonw ? MM_STAT_FONW_MASK : 0);
|
|
return std::make_shared<DtbPageFault>(req->getVaddr(),
|
|
req->getFlags(),
|
|
flags);
|
|
}
|
|
if (entry->fonw) {
|
|
write_acv++;
|
|
uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK;
|
|
return std::make_shared<DtbPageFault>(req->getVaddr(),
|
|
req->getFlags(),
|
|
flags);
|
|
}
|
|
} else {
|
|
if (!(entry->xre & MODE2MASK(mode))) {
|
|
read_acv++;
|
|
uint64_t flags = MM_STAT_ACV_MASK |
|
|
(entry->fonr ? MM_STAT_FONR_MASK : 0);
|
|
return std::make_shared<DtbAcvFault>(req->getVaddr(),
|
|
req->getFlags(),
|
|
flags);
|
|
}
|
|
if (entry->fonr) {
|
|
read_acv++;
|
|
uint64_t flags = MM_STAT_FONR_MASK;
|
|
return std::make_shared<DtbPageFault>(req->getVaddr(),
|
|
req->getFlags(),
|
|
flags);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (write)
|
|
write_hits++;
|
|
else
|
|
read_hits++;
|
|
}
|
|
|
|
// check that the physical address is ok (catch bad physical addresses)
|
|
if (req->getPaddr() & ~PAddrImplMask) {
|
|
return std::make_shared<MachineCheckFault>();
|
|
}
|
|
|
|
return checkCacheability(req);
|
|
}
|
|
|
|
TlbEntry &
|
|
TLB::index(bool advance)
|
|
{
|
|
TlbEntry *entry = &table[nlu];
|
|
|
|
if (advance)
|
|
nextnlu();
|
|
|
|
return *entry;
|
|
}
|
|
|
|
Fault
|
|
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
|
|
{
|
|
if (mode == Execute)
|
|
return translateInst(req, tc);
|
|
else
|
|
return translateData(req, tc, mode == Write);
|
|
}
|
|
|
|
void
|
|
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
|
|
Translation *translation, Mode mode)
|
|
{
|
|
assert(translation);
|
|
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
|
|
}
|
|
|
|
Fault
|
|
TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
|
|
{
|
|
panic("Not implemented\n");
|
|
return NoFault;
|
|
}
|
|
|
|
Fault
|
|
TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
|
|
{
|
|
return NoFault;
|
|
}
|
|
|
|
} // namespace AlphaISA
|
|
|
|
AlphaISA::TLB *
|
|
AlphaTLBParams::create()
|
|
{
|
|
return new AlphaISA::TLB(this);
|
|
}
|