1196 lines
138 KiB
Text
1196 lines
138 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.922414 # Number of seconds simulated
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sim_ticks 1922413663500 # Number of ticks simulated
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final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 912210 # Simulator instruction rate (inst/s)
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host_op_rate 912209 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 31217732593 # Simulator tick rate (ticks/s)
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host_mem_usage 318584 # Number of bytes of host memory used
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host_seconds 61.58 # Real time elapsed on the host
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sim_insts 56174594 # Number of instructions simulated
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sim_ops 56174594 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 401737 # Number of read requests accepted
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system.physmem.writeReqs 157245 # Number of write requests accepted
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system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue
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system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 25230 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25660 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25603 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25523 # Per bank write bursts
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system.physmem.perBankRdBursts::4 24970 # Per bank write bursts
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system.physmem.perBankRdBursts::5 24976 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24206 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24492 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25173 # Per bank write bursts
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system.physmem.perBankRdBursts::9 24777 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25267 # Per bank write bursts
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system.physmem.perBankRdBursts::11 24875 # Per bank write bursts
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system.physmem.perBankRdBursts::12 24505 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25378 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25651 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25357 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8677 # Per bank write bursts
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system.physmem.perBankWrBursts::1 8490 # Per bank write bursts
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system.physmem.perBankWrBursts::2 8972 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8549 # Per bank write bursts
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system.physmem.perBankWrBursts::4 8030 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7962 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7256 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7133 # Per bank write bursts
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system.physmem.perBankWrBursts::8 8241 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7447 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7887 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7738 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8187 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8962 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8876 # Per bank write bursts
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system.physmem.perBankWrBursts::15 8644 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
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system.physmem.totGap 1922401791500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 401737 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 157245 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 2057087750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 360176 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 107764 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3439112.16 # Average gap between requests
|
|
system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 670.677845 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 670.732006 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 9063642 # DTB read hits
|
|
system.cpu.dtb.read_misses 10324 # DTB read misses
|
|
system.cpu.dtb.read_acv 210 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 728853 # DTB read accesses
|
|
system.cpu.dtb.write_hits 6355525 # DTB write hits
|
|
system.cpu.dtb.write_misses 1142 # DTB write misses
|
|
system.cpu.dtb.write_acv 157 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
|
system.cpu.dtb.data_hits 15419167 # DTB hits
|
|
system.cpu.dtb.data_misses 11466 # DTB misses
|
|
system.cpu.dtb.data_acv 367 # DTB access violations
|
|
system.cpu.dtb.data_accesses 1020784 # DTB accesses
|
|
system.cpu.itb.fetch_hits 4974414 # ITB hits
|
|
system.cpu.itb.fetch_misses 5010 # ITB misses
|
|
system.cpu.itb.fetch_acv 184 # ITB acv
|
|
system.cpu.itb.fetch_accesses 4979424 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.numCycles 3844827327 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 56174594 # Number of instructions committed
|
|
system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
|
system.cpu.num_func_calls 1483106 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 52047018 # number of integer instructions
|
|
system.cpu.num_fp_insts 324460 # number of float instructions
|
|
system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 15471782 # number of memory refs
|
|
system.cpu.num_load_insts 9100493 # Number of load instructions
|
|
system.cpu.num_store_insts 6371289 # Number of store instructions
|
|
system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.933046 # Percentage of idle cycles
|
|
system.cpu.Branches 8421188 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 56186427 # Class of executed instruction
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
|
|
system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed
|
|
system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.kern.syscall::total 326 # number of syscalls executed
|
|
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed
|
|
system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
|
|
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
|
|
system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.callpal::total 192894 # number of callpals executed
|
|
system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
|
|
system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
|
|
system.cpu.kern.mode_good::kernel 1910
|
|
system.cpu.kern.mode_good::user 1740
|
|
system.cpu.kern.mode_good::idle 170
|
|
system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
|
system.cpu.dcache.tags.replacements 1391374 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 13664105 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1374617 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 42596747630 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 42596747630 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 42596747630 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 8882773 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 8882773 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6155949 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6155949 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199234 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 199234 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 15038722 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 15038722 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 15038722 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 15038722 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120486 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.120486 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086325 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086325 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.091405 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 835634 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.091405 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 928205 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.992326 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.992326 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 57115304 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 57115304 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 55257552 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 55257552 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 55257552 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 55257552 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 55257552 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 55257552 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 928876 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 928876 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 928876 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 928876 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 928876 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 928876 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 13004894000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 13004894000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 13004894000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 13004894000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 13004894000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 13004894000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 56186428 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 56186428 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 56186428 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 56186428 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 56186428 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 56186428 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14000.678239 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14000.678239 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14000.678239 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14000.678239 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928876 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 928876 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 928876 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 928876 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 928876 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 928876 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11606411000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 11606411000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11606411000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 11606411000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11606411000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 11606411000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12495.113449 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12495.113449 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 336253 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65287.674931 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2448546 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 401415 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 6.099787 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 7245222750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4753.205077 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 5018.688389 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.847104 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072528 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.076579 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.996211 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4937 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3234 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55805 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 25957144 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 25957144 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 915565 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 815571 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1731136 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 835634 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 835634 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 187495 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 187495 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 915565 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1003066 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1918631 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 915565 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1003066 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1918631 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 271964 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 116857 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 116857 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 388821 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 402112 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 388821 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 402112 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1064072500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19718835000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 20782907500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220998 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 220998 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8916531881 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8916531881 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1064072500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 28635366881 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 29699439381 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1064072500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 28635366881 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 29699439381 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 928856 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1087535 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2016391 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 835634 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 835634 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304352 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 304352 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 928856 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1391887 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2320743 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 928856 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1391887 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2320743 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014309 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250074 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.141468 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383953 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.383953 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014309 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279348 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.173269 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014309 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279348 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.173269 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80059.626815 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72505.313203 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72857.294351 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16999.846154 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16999.846154 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76302.933337 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76302.933337 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 73858.624913 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 73858.624913 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 74181 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271964 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 41937 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3214755 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1.012990 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.113233 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 3172994 98.70% 98.70% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 41761 1.30% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3214755 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 9650 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41685 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375525 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
|
|
system.iocache.overall_misses::total 173 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
|
system.iocache.writebacks::total 41512 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 292358 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 292358 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 9650 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 9650 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 115693 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 116738 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 116738 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 431 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 576169 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 576169 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 576169 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
---------- End Simulation Statistics ----------
|