Andreas Sandberg 7e25052fee Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming ... Changeset 4f54b0f229b5 removed the call to doDrain in changeToTiming based on the assumption that the system does not need draining when running in atomic mode. This is a false assumption since at least the System class requires the system to be drained before it allows switching of memory modes. This patch reverts that part of the changeset.		2012-11-02 11:32:00 -05:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	Regression: Use CPU clock and 32-byte width for L1-L2 bus	2012-10-15 08:08:08 -04:00
Caches.py	config: Unify caches used in regressions and adjust L2 MSHRs	2012-10-30 07:44:08 -04:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	config: Use SimpleDRAM in full-system, and with o3 and inorder	2012-10-25 13:14:38 -04:00
O3_ARM_v7a.py	Mem: Use cycles to express cache-related latencies	2012-10-15 08:10:54 -04:00
Options.py	se.py: support specifying multiple programs via command line	2012-09-09 09:33:45 -05:00
Simulation.py	Partly revert [4f54b0f229b5] and move draining to m5.changeToTiming	2012-11-02 11:32:00 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00