ab9c20cc78
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions that were run, the sims are about 2x speedup from changeset 7726 which is the last change since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
283 lines
31 KiB
Plaintext
283 lines
31 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 94112 # Simulator instruction rate (inst/s)
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host_mem_usage 191540 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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host_tick_rate 346291258 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 5827 # Number of instructions simulated
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sim_seconds 0.000022 # Number of seconds simulated
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sim_ticks 21538000 # Number of ticks simulated
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system.cpu.AGEN-Unit.agens 2404 # Number of Address Generations
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system.cpu.Branch-Predictor.BTBHitPct 14.054054 # BTB Hit Percentage
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system.cpu.Branch-Predictor.BTBHits 26 # Number of BTB hits
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system.cpu.Branch-Predictor.BTBLookups 185 # Number of BTB lookups
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system.cpu.Branch-Predictor.RASInCorrect 30 # Number of incorrect RAS predictions.
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system.cpu.Branch-Predictor.condIncorrect 844 # Number of conditional branches incorrect
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system.cpu.Branch-Predictor.condPredicted 778 # Number of conditional branches predicted
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system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups
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system.cpu.Branch-Predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False).
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system.cpu.Branch-Predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True).
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system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target.
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system.cpu.Execution-Unit.executions 3261 # Number of Instructions Executed.
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system.cpu.Execution-Unit.mispredictPct 92.139738 # Percentage of Incorrect Branches Predicts
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system.cpu.Execution-Unit.mispredicted 844 # Number of Branches Incorrectly Predicted
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system.cpu.Execution-Unit.predicted 72 # Number of Branches Incorrectly Predicted
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system.cpu.Execution-Unit.predictedNotTakenIncorrect 812 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.Execution-Unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed
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system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed
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system.cpu.RegFile-Manager.regFileAccesses 10004 # Number of Total Accesses (Read+Write) to the Register File
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system.cpu.RegFile-Manager.regFileReads 6594 # Number of Reads from Register File
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system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File
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system.cpu.RegFile-Manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic
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system.cpu.activity 13.954082 # Percentage of cycles cpu is active
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system.cpu.comBranches 916 # Number of Branches instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.comInts 2155 # Number of Integer instructions committed
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system.cpu.comLoads 1164 # Number of Load instructions committed
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system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
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system.cpu.comNops 657 # Number of Nop instructions committed
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system.cpu.comStores 925 # Number of Store instructions committed
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system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
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system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.cpi 7.392655 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.cpi_total 7.392655 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56676.136364 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53678.160920 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 4987500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.075601 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 4670000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 55935.483871 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53637.254902 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 832 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 5202000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.100541 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 93 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 42 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2735500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 53100 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 13.826087 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 265500 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56295.580110 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 10189500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.086644 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 181 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 7405500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.021745 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 89.067186 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56295.580110 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 1908 # number of overall hits
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system.cpu.dcache.overall_miss_latency 10189500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.086644 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 181 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 43 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 7405500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 89.067186 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1908 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55527.559055 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 472 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 21156000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.446659 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 16957000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.373974 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 31000 # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1.479624 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 62000 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 853 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55527.559055 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency
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system.cpu.icache.demand_hits 472 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 21156000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.446659 # miss rate for demand accesses
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system.cpu.icache.demand_misses 381 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 62 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 16957000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.373974 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.070945 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 145.295903 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55527.559055 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 472 # number of overall hits
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system.cpu.icache.overall_miss_latency 21156000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.446659 # miss rate for overall accesses
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system.cpu.icache.overall_misses 381 # number of overall misses
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system.cpu.icache.overall_mshr_hits 62 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 16957000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.373974 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 13 # number of replacements
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system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 145.295903 # Cycle average of tags in use
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system.cpu.icache.total_refs 472 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 37066 # Number of cycles cpu's stages were not processed
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system.cpu.ipc 0.135269 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.ipc_total 0.135269 # IPC: Total IPC of All Threads
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52470.588235 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40235.294118 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 2676000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2052000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52357.673267 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40153.465347 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 21152500 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 16222000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52370.329670 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 23828500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 18274000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::0 0.006169 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::0 202.151439 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52370.329670 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 2 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 23828500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 455 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 18274000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 202.151439 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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|
system.cpu.numCycles 43077 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.runCycles 6011 # Number of cycles cpu stages are processed.
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
|
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
|
system.cpu.stage-0.idleCycles 39203 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-0.runCycles 3874 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-0.utilization 8.993198 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-1.idleCycles 40159 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-1.runCycles 2918 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-1.utilization 6.773916 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-2.idleCycles 40245 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-2.runCycles 2832 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-2.utilization 6.574274 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-3.idleCycles 41757 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-3.runCycles 1320 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-3.utilization 3.064280 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-4.idleCycles 39874 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-4.runCycles 3203 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-4.utilization 7.435522 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.threadCycles 10193 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|