gem5/src/arch/mips
Akash Bagdia 7d7ab73862 sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
2013-06-27 05:49:49 -04:00
..
bare_iron MIPS: Many style fixes. 2009-07-21 01:08:53 -07:00
isa scons: Add warning for missing declarations 2013-02-19 05:56:07 -05:00
linux ISA: generic Linux thread info support 2012-11-02 11:32:00 -05:00
decoder.cc ISA,CPU: Generalize and split out the components of the decode cache. 2012-05-26 13:45:12 -07:00
decoder.hh x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch 2013-01-22 00:10:10 -06:00
dsp.cc SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
dsp.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
dt_constants.hh MIPS: Use BitUnions instead of bits() functions and constants. 2009-07-20 20:14:15 -07:00
faults.cc Merge with head, hopefully the last time for this batch. 2012-01-31 22:40:08 -08:00
faults.hh Merge with head, hopefully the last time for this batch. 2012-01-31 22:40:08 -08:00
idle_event.cc MIPS: Many style fixes. 2009-07-21 01:08:53 -07:00
idle_event.hh fix MIPS headers 2007-11-15 14:21:01 -05:00
interrupts.cc SE/FS: Build the Interrupt objects in SE mode. 2011-10-09 00:15:50 -07:00
interrupts.hh MIPS: Get MIPS_FS to compile, more style fixes. 2009-07-21 01:09:05 -07:00
isa.cc arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
isa.hh scons: Add warning for overloaded virtual functions 2013-02-19 05:56:07 -05:00
isa_traits.hh ISA: generic Linux thread info support 2012-11-02 11:32:00 -05:00
kernel_stats.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
locked_mem.hh o3: Fix issue with LLSC ordering and speculation 2013-01-07 13:05:33 -05:00
microcode_rom.hh CPU: Create a microcode ROM object in the CPU which is defined by the ISA. 2008-10-12 15:59:21 -07:00
MipsCPU.py python: Move more code into m5.util allow SCons to use that code. 2009-09-22 15:24:16 -07:00
MipsInterrupts.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
MipsISA.py arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
MipsSystem.py sim: Add the notion of clock domains to all ClockedObjects 2013-06-27 05:49:49 -04:00
MipsTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
mmapped_ipr.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
mt.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
mt_constants.hh MIPS: Use BitUnions instead of bits() functions and constants. 2009-07-20 20:14:15 -07:00
pagetable.cc MIPS: Many style fixes. 2009-07-21 01:08:53 -07:00
pagetable.hh SE/FS: Turn on the page table class in FS. 2011-10-16 05:06:40 -07:00
pra_constants.hh MIPS: Get MIPS_FS to compile, more style fixes. 2009-07-21 01:09:05 -07:00
process.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
process.hh scons: Add warning for overloaded virtual functions 2013-02-19 05:56:06 -05:00
registers.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
remote_gdb.cc Decode: Make the Decoder class defined per ISA. 2012-05-25 00:53:37 -07:00
remote_gdb.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
SConscript arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
SConsopts go back and fix up MIPS copyright headers 2007-11-16 21:32:22 -05:00
stacktrace.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
system.cc Checkpoint: Make system serialize call children 2012-10-15 08:12:29 -04:00
system.hh Checkpoint: Make system serialize call children 2012-10-15 08:12:29 -04:00
tlb.cc arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
tlb.hh arch: Create a method to finalize physical addresses 2013-06-03 13:55:41 +02:00
types.hh mips: cleanup ISA-specific code 2011-03-26 09:23:52 -04:00
utility.cc Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
utility.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
vtophys.cc Merge with the main repo. 2012-01-28 07:24:01 -08:00
vtophys.hh Merge with main repository. 2012-01-30 21:07:57 -08:00