Jiuyue Ma 7d03bf4d6b config, x86: swap bus_id of ISA/PCI in X86 IntelMPTable ... This patch assign bus_id=0 to PCI bus and bus_id=1 to ISA bus for X86 platform. Because PCI device get config space address using Pc::calcPciConfigAddr() which requires "assert(bus==0)". This fixes PCI interrupt routing and discovery on Linux. Committed by: Nilay Vaish <nilay@cs.wisc.edu>		2014-07-17 11:00:12 +08:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	mem: Rename Bus to XBar to better reflect its behaviour	2014-09-20 17:18:32 -04:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
FSConfig.py	config, x86: swap bus_id of ISA/PCI in X86 IntelMPTable	2014-07-17 11:00:12 +08:00
MemConfig.py	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	2014-03-23 11:12:12 -04:00
O3_ARM_v7a.py	cpu: Change writeback modeling for outstanding instructions	2014-09-03 07:42:33 -04:00
Options.py	config: add num-work-ids command line option	2014-04-10 13:43:33 -05:00
Simulation.py	config: add num-work-ids command line option	2014-04-10 13:43:33 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00