gem5/src/mem/cache/prefetch
Andreas Hansson 7cd49b24d2 sim: Make clock private and access using clockPeriod()
This patch makes the clock member private to the ClockedObject and
forces all children to access it using clockPeriod(). This makes it
impossible to inadvertently change the clock, and also makes it easier
to transition to a situation where the clock is derived from e.g. a
clock domain, or through a multiplier.
2013-02-19 05:56:06 -05:00
..
base.cc sim: Make clock private and access using clockPeriod() 2013-02-19 05:56:06 -05:00
base.hh Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
ghb.cc Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
ghb.hh Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
Prefetcher.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
SConscript prefetcher: Make prefetcher a sim object instead of it being a parameter on cache 2012-02-12 16:07:38 -06:00
stride.cc Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
stride.hh Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
tagged.cc Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
tagged.hh Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00