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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt
Andreas Sandberg 447a6b6442 stats: Update switcheroo reference stats 
The Minor draining fixes affect perturb the timing slightly since it
affects how the simulator is drained. Update reference statistics to
reflect this expected change.
2015-07-31 17:04:59 +01:00

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---------- Begin Simulation Statistics ----------
sim_seconds 51.316635 # Number of seconds simulated
sim_ticks 51316634750000 # Number of ticks simulated
final_tick 51316634750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 555955 # Simulator instruction rate (inst/s)
host_op_rate 653275 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 33346498264 # Simulator tick rate (ticks/s)
host_mem_usage 678992 # Number of bytes of host memory used
host_seconds 1538.89 # Real time elapsed on the host
sim_insts 855554018 # Number of instructions simulated
sim_ops 1005318688 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 87040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 2475252 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 44191944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 26688 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 26112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 701824 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 6588352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 27264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 1769600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 8688000 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 64576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.itb.walker 58944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 1797376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 16165440 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 417344 # Number of bytes read from this memory
system.physmem.bytes_read::total 83195260 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 2475252 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 701824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 1769600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 1797376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6744052 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 70299712 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 70320292 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 79083 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 690512 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 417 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 408 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10966 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 102943 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 426 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 363 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 27650 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 135750 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 1009 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.itb.walker 921 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 28084 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 252585 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6521 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1340346 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1098433 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1101006 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 1681 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1696 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 48235 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 861162 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 520 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 509 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 13676 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 128386 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 531 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 453 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 34484 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 169302 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1258 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.itb.walker 1149 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 35025 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 315014 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8133 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1621214 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 48235 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 13676 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 34484 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 35025 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 131420 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1369921 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1370322 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1369921 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 1681 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1696 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 48235 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 861563 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 520 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 13676 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 128386 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 531 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 453 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 34484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 169302 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1258 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.itb.walker 1149 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 35025 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 315014 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8133 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2991536 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 565119 # Number of read requests accepted
system.physmem.writeReqs 485303 # Number of write requests accepted
system.physmem.readBursts 565119 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 485303 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 36124864 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 42752 # Total number of bytes read from write queue
system.physmem.bytesWritten 31057472 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 36167616 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 31059392 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 668 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 65964 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 37092 # Per bank write bursts
system.physmem.perBankRdBursts::1 38221 # Per bank write bursts
system.physmem.perBankRdBursts::2 34232 # Per bank write bursts
system.physmem.perBankRdBursts::3 34199 # Per bank write bursts
system.physmem.perBankRdBursts::4 32555 # Per bank write bursts
system.physmem.perBankRdBursts::5 36931 # Per bank write bursts
system.physmem.perBankRdBursts::6 31211 # Per bank write bursts
system.physmem.perBankRdBursts::7 33972 # Per bank write bursts
system.physmem.perBankRdBursts::8 32403 # Per bank write bursts
system.physmem.perBankRdBursts::9 38255 # Per bank write bursts
system.physmem.perBankRdBursts::10 35917 # Per bank write bursts
system.physmem.perBankRdBursts::11 41761 # Per bank write bursts
system.physmem.perBankRdBursts::12 35252 # Per bank write bursts
system.physmem.perBankRdBursts::13 36878 # Per bank write bursts
system.physmem.perBankRdBursts::14 32220 # Per bank write bursts
system.physmem.perBankRdBursts::15 33352 # Per bank write bursts
system.physmem.perBankWrBursts::0 29650 # Per bank write bursts
system.physmem.perBankWrBursts::1 31742 # Per bank write bursts
system.physmem.perBankWrBursts::2 28889 # Per bank write bursts
system.physmem.perBankWrBursts::3 30829 # Per bank write bursts
system.physmem.perBankWrBursts::4 29399 # Per bank write bursts
system.physmem.perBankWrBursts::5 32279 # Per bank write bursts
system.physmem.perBankWrBursts::6 27374 # Per bank write bursts
system.physmem.perBankWrBursts::7 30609 # Per bank write bursts
system.physmem.perBankWrBursts::8 28675 # Per bank write bursts
system.physmem.perBankWrBursts::9 32426 # Per bank write bursts
system.physmem.perBankWrBursts::10 29991 # Per bank write bursts
system.physmem.perBankWrBursts::11 34263 # Per bank write bursts
system.physmem.perBankWrBursts::12 30290 # Per bank write bursts
system.physmem.perBankWrBursts::13 31646 # Per bank write bursts
system.physmem.perBankWrBursts::14 28165 # Per bank write bursts
system.physmem.perBankWrBursts::15 29046 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
system.physmem.totGap 51315634470500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 565119 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 485303 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 399408 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 101730 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 37111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 23215 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 366 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 278 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 258 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 310 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 421 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 535 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 237 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 87 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 82 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 65 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 46 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 586 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 571 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 566 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 563 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 562 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 564 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 560 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 559 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 552 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 546 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 7847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 8616 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 19482 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 23454 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 26479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 28098 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 28044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 29307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 29679 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 31078 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 30832 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 30867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 29853 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 30684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 32884 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 28794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 28945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 27599 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 209 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 226 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 278814 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 240.955476 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 145.236301 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 282.316846 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 127586 45.76% 45.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 69517 24.93% 70.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 25415 9.12% 79.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12865 4.61% 84.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 9508 3.41% 87.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5843 2.10% 89.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 4935 1.77% 91.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3869 1.39% 93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 19276 6.91% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 278814 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 27347 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.639193 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 13.469110 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-31 24770 90.58% 90.58% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32-63 2374 8.68% 99.26% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::64-95 169 0.62% 99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::96-127 20 0.07% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::128-159 3 0.01% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::160-191 2 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::192-223 2 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::224-255 2 0.01% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::320-351 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::704-735 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::736-767 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::928-959 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 27347 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 27347 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.745018 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.170209 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.144032 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 15 0.05% 0.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 12 0.04% 0.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 8 0.03% 0.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 33 0.12% 0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 25607 93.64% 93.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 450 1.65% 95.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 306 1.12% 96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 171 0.63% 97.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 124 0.45% 97.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 194 0.71% 98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 52 0.19% 98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 11 0.04% 98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 30 0.11% 98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 23 0.08% 98.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 22 0.08% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 11 0.04% 98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 180 0.66% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 15 0.05% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 25 0.09% 99.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 19 0.07% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 6 0.02% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 14 0.05% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 3 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 27347 # Writes before turning the bus around for reads
system.physmem.totQLat 11691794846 # Total ticks spent queuing
system.physmem.totMemAccLat 22275251096 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2822255000 # Total ticks spent in databus transfers
system.physmem.avgQLat 20713.57 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 39463.57 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 0.70 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.61 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 0.70 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.61 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 8.89 # Average write queue length when enqueuing
system.physmem.readRowHits 432443 # Number of row buffer hits during reads
system.physmem.writeRowHits 338466 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.61 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 69.74 # Row buffer hit rate for writes
system.physmem.avgGap 48852398.82 # Average gap between requests
system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1049600160 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 571056750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2171551200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 1560196080 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3312990217680 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1178995763115 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29844954866250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34342293251235 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.290653 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 48908598729306 # Time in different power states
system.physmem_0.memoryStateTime::REF 1693757780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 121315217444 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 1058233680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 575746875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2231096400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 1584372960 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3312990217680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1180768405545 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 30633804913500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 35133012986640 # Total energy per rank (pJ)
system.physmem_1.averagePower 665.617184 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 48905982752444 # Time in different power states
system.physmem_1.memoryStateTime::REF 1693757780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 123922534306 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 91446 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 91446 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 91446 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 91446 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 91446 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 388607264328 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.523233 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -203332229172 -52.32% -52.32% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 591939493500 152.32% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 388607264328 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 66855 84.61% 84.61% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 12161 15.39% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 79016 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91446 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91446 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 79016 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 79016 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 170462 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 64637193 # DTB read hits
system.cpu0.dtb.read_misses 69043 # DTB read misses
system.cpu0.dtb.write_hits 58569418 # DTB write hits
system.cpu0.dtb.write_misses 22403 # DTB write misses
system.cpu0.dtb.flush_tlb 1193 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 16284 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 407 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 42446 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2875 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 7756 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 64706236 # DTB read accesses
system.cpu0.dtb.write_accesses 58591821 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 123206611 # DTB hits
system.cpu0.dtb.misses 91446 # DTB misses
system.cpu0.dtb.accesses 123298057 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 53719 # Table walker walks requested
system.cpu0.itb.walker.walksLong 53719 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples 53719 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 53719 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 53719 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 388607264328 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.523329 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -203369594172 -52.33% -52.33% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 591976858500 152.33% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 388607264328 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 46750 94.94% 94.94% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2490 5.06% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 49240 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53719 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53719 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49240 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49240 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 102959 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 343542724 # ITB inst hits
system.cpu0.itb.inst_misses 53719 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1193 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 16284 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 407 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 30063 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 343596443 # ITB inst accesses
system.cpu0.itb.hits 343542724 # DTB hits
system.cpu0.itb.misses 53719 # DTB misses
system.cpu0.itb.accesses 343596443 # DTB accesses
system.cpu0.numCycles 414507923 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 343392928 # Number of instructions committed
system.cpu0.committedOps 403926056 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 371010641 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 350352 # Number of float alu accesses
system.cpu0.num_func_calls 20655596 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 52208909 # number of instructions that are conditional controls
system.cpu0.num_int_insts 371010641 # number of integer instructions
system.cpu0.num_fp_insts 350352 # number of float instructions
system.cpu0.num_int_register_reads 542983655 # number of times the integer registers were read
system.cpu0.num_int_register_writes 294627893 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 558017 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 311708 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 89970579 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 89777589 # number of times the CC registers were written
system.cpu0.num_mem_refs 123282310 # number of memory refs
system.cpu0.num_load_insts 64695790 # Number of load instructions
system.cpu0.num_store_insts 58586520 # Number of store instructions
system.cpu0.num_idle_cycles 404635948.136490 # Number of idle cycles
system.cpu0.num_busy_cycles 9871974.863510 # Number of busy cycles
system.cpu0.not_idle_fraction 0.023816 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.976184 # Percentage of idle cycles
system.cpu0.Branches 76586966 # Number of branches fetched
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 279907726 69.26% 69.26% # Class of executed instruction
system.cpu0.op_class::IntMult 889275 0.22% 69.48% # Class of executed instruction
system.cpu0.op_class::IntDiv 42026 0.01% 69.49% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 46880 0.01% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
system.cpu0.op_class::MemRead 64695790 16.01% 85.50% # Class of executed instruction
system.cpu0.op_class::MemWrite 58586520 14.50% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 404168217 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 16558 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 9753179 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 295582609 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 9753691 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 30.304693 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.786963 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.350548 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.889749 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 3.972456 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970287 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010450 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011503 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.007759 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1252278840 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1252278840 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 60369359 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 19140658 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 26830987 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 45818234 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 152159238 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 55384084 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 17587575 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 23765695 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 38719665 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 135457019 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 164079 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 46225 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 81077 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 111985 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 403366 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 132348 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44500 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu2.data 54331 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu3.data 98773 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 329952 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1446319 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 438478 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 586341 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 962737 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3433875 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1538701 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 475697 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 636200 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1104802 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 3755400 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 115753443 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 36728233 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 50596682 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 84537899 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 287616257 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 115917522 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 36774458 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 50677759 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 84649884 # number of overall hits
system.cpu0.dcache.overall_hits::total 288019623 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 2092041 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 624638 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 970441 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 3415331 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7102451 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 840568 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 251537 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 625226 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 3495089 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 5212420 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 514907 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 141320 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 198621 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 334446 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1189294 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 668357 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 105494 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu2.data 155232 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu3.data 298331 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1227414 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 93062 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37431 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 50097 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 180259 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 360849 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 4 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2932609 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 876175 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1595667 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 6910420 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 12314871 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 3447516 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 1017495 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1794288 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 7244866 # number of overall misses
system.cpu0.dcache.overall_misses::total 13504165 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9754171500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15346689000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 52027511000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 77128371500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6989966000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 16964216500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96846252035 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 120800434535 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2685222500 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 4289017000 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 10724214307 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 17698453807 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 525769500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 711390500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2241356000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 3478516000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 142500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 142500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 16744137500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 32310905500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 148873763035 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 197928806035 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 16744137500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 32310905500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 148873763035 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 197928806035 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 62461400 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 19765296 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 27801428 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 49233565 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 159261689 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56224652 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 17839112 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 24390921 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 42214754 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 140669439 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 678986 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 187545 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 279698 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 446431 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1592660 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 800705 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 149994 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 209563 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 397104 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1557366 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1539381 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 475909 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 636438 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1142996 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 3794724 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1538701 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 475697 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 636200 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1104806 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 3755404 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 118686052 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 37604408 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 52192349 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 91448319 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 299931128 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 119365038 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 37791953 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 52472047 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 91894750 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 301523788 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033493 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031603 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.034906 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.069370 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.044596 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014950 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014100 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025634 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.082793 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.037054 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758347 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.753526 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.710127 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.749155 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.746734 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.834711 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.703321 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.740741 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.751267 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788135 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060454 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078652 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.078715 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.157707 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095092 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024709 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023300 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030573 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.075566 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.041059 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028882 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026924 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034195 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.078839 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.044786 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15615.719024 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15814.139139 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15233.519387 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10859.402128 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27789.017123 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27132.935131 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27709.237743 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 23175.499007 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25453.793581 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 27629.721965 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35947.368215 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14419.302539 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14046.365312 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14200.261493 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12434.086509 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9639.810558 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 35625 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 35625 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19110.494479 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20249.153175 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21543.374069 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 16072.340996 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16456.235657 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18007.647323 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20548.863572 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14656.871123 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 12269651 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 11721 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 884921 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 303 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.865250 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 38.683168 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 7530303 # number of writebacks
system.cpu0.dcache.writebacks::total 7530303 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3244 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 107323 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1868973 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 1979540 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2183 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 273456 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2901507 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 3177146 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 23 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2180 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 2203 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8289 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 11291 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 111071 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 130651 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 5427 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 380779 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 4770480 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 5156686 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 5427 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 380779 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 4770480 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 5156686 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 621394 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 863118 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1546358 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3030870 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 249354 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 351770 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 593582 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1194706 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 141097 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 198504 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 329326 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 668927 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 105494 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 155209 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 296151 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 556854 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29142 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 38806 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 69188 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137136 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 4 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 870748 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 1214888 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 2139940 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 4225576 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1011845 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 1413392 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 2469266 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4894503 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6330 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4869 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4820 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16019 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5775 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4397 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4483 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14655 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 12105 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 9266 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 9303 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30674 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9061716000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12702209500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23634658500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45398584000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6664052500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9037887500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17334765406 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33036705406 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2466765500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2966502500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 5024621000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10457889000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2579728500 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4133451000 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10340882807 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 17054062307 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 376111500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 502612000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 917608500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1796332000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 138500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 138500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 15725768500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 21740097000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 40969423906 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 78435289406 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 18192534000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 24706599500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 45994044906 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 88893178406 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1115432000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 821405500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 838200500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2775038000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1040608000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 744829000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 810242500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2595679500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2156040000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1566234500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1648443000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5370717500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031439 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031046 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031409 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019031 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013978 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014422 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014061 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008493 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752337 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.709708 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.737686 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.420006 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.703321 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.740632 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.745777 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.357561 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061234 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060974 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060532 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036139 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023155 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023277 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023401 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.014088 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026774 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026936 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.026871 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.016233 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14582.883002 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14716.654617 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15284.079431 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14978.730200 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26725.268093 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25692.604543 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29203.657466 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27652.581812 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17482.763631 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14944.295833 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15257.286093 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15633.827010 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24453.793581 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26631.516214 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34917.602193 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30625.733688 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12906.166358 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12951.914652 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13262.538301 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13098.909112 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34625 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34625 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18060.068470 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17894.733506 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 19145.127390 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18562.034952 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17979.566040 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17480.358952 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18626.606006 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18161.839600 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176213.586098 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168701.067981 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 173900.518672 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173234.159436 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180191.861472 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 169394.814646 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180736.671872 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177119.037871 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178111.524164 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 169030.271962 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177194.775879 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175090.222990 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 15815402 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.974774 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 560516546 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 15815914 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.440035 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10320548500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 470.983323 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.370310 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.740928 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 11.880214 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.919889 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006583 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.050275 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.023204 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 592508619 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 592508619 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 338062772 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 107390355 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 66013680 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 49049739 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 560516546 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 338062772 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 107390355 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 66013680 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 49049739 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 560516546 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 338062772 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 107390355 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 66013680 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 49049739 # number of overall hits
system.cpu0.icache.overall_hits::total 560516546 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 5529192 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 1696190 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 3915157 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 5035545 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 16176084 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 5529192 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 1696190 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 3915157 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 5035545 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 16176084 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 5529192 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 1696190 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 3915157 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 5035545 # number of overall misses
system.cpu0.icache.overall_misses::total 16176084 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22827874500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 52925900000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 65832917354 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 141586691854 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 22827874500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 52925900000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 65832917354 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 141586691854 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 22827874500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 52925900000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 65832917354 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 141586691854 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 343591964 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 109086545 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 69928837 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 54085284 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 576692630 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 343591964 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 109086545 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 69928837 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 54085284 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 576692630 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 343591964 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 109086545 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 69928837 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 54085284 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 576692630 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016092 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015549 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.055988 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.093104 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.028050 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016092 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015549 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.055988 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.093104 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.028050 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016092 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015549 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.055988 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.093104 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.028050 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13458.323950 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13518.206294 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13073.642943 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 8752.841037 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13458.323950 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13518.206294 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13073.642943 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 8752.841037 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13458.323950 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13518.206294 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13073.642943 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 8752.841037 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 40592 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 3092 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.128072 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 360095 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 360095 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 360095 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 360095 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 360095 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 360095 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1696190 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3915157 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4675450 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 10286797 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 1696190 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 3915157 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 4675450 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 10286797 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 1696190 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 3915157 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 4675450 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 10286797 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21131684500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 49010743000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58303327383 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 128445754883 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21131684500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 49010743000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58303327383 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 128445754883 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21131684500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 49010743000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58303327383 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 128445754883 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055988 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.086446 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017838 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055988 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.086446 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.017838 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055988 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.086446 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.017838 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12458.323950 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12518.206294 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12470.099645 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12486.467351 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12458.323950 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12518.206294 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12470.099645 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12486.467351 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12458.323950 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12518.206294 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12470.099645 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12486.467351 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 31331 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 31331 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4585 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22783 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 31326 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 31326 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 31326 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 27373 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 24398.385270 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 21301.040403 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 13057.600682 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 17904 65.41% 65.41% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9272 33.87% 99.28% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 108 0.39% 99.67% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 61 0.22% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 5 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 27373 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 2726095120 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.627697 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.483419 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1014934000 37.23% 37.23% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 1711161120 62.77% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 2726095120 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 22783 83.25% 83.25% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 4585 16.75% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 27368 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31331 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31331 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27368 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27368 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 58699 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 20435080 # DTB read hits
system.cpu1.dtb.read_misses 24017 # DTB read misses
system.cpu1.dtb.write_hits 18473169 # DTB write hits
system.cpu1.dtb.write_misses 7314 # DTB write misses
system.cpu1.dtb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 5397 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 130 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 17737 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 965 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 2574 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 20459097 # DTB read accesses
system.cpu1.dtb.write_accesses 18480483 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 38908249 # DTB hits
system.cpu1.dtb.misses 31331 # DTB misses
system.cpu1.dtb.accesses 38939580 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 20082 # Table walker walks requested
system.cpu1.itb.walker.walksLong 20082 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 956 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17736 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 20082 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 20082 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 20082 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 18692 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 27635.592767 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24782.304535 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 14713.760053 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 9635 51.55% 51.55% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 8833 47.26% 98.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 80 0.43% 99.23% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 115 0.62% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.85% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 12 0.06% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 3 0.02% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 3 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 18692 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 17736 94.89% 94.89% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 956 5.11% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 18692 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20082 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20082 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18692 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18692 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 38774 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 109086545 # ITB inst hits
system.cpu1.itb.inst_misses 20082 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 5397 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 130 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 13123 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 109106627 # ITB inst accesses
system.cpu1.itb.hits 109086545 # DTB hits
system.cpu1.itb.misses 20082 # DTB misses
system.cpu1.itb.accesses 109106627 # DTB accesses
system.cpu1.numCycles 1184099170 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 109009230 # Number of instructions committed
system.cpu1.committedOps 127862448 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 117464588 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 115738 # Number of float alu accesses
system.cpu1.num_func_calls 6440342 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 16554986 # number of instructions that are conditional controls
system.cpu1.num_int_insts 117464588 # number of integer instructions
system.cpu1.num_fp_insts 115738 # number of float instructions
system.cpu1.num_int_register_reads 169322185 # number of times the integer registers were read
system.cpu1.num_int_register_writes 93148708 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 190671 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 89412 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 28259298 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 28158154 # number of times the CC registers were written
system.cpu1.num_mem_refs 38905190 # number of memory refs
system.cpu1.num_load_insts 20434165 # Number of load instructions
system.cpu1.num_store_insts 18471025 # Number of store instructions
system.cpu1.num_idle_cycles 1158563290.473996 # Number of idle cycles
system.cpu1.num_busy_cycles 25535879.526004 # Number of busy cycles
system.cpu1.not_idle_fraction 0.021566 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.978434 # Percentage of idle cycles
system.cpu1.Branches 24332682 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 88740475 69.36% 69.36% # Class of executed instruction
system.cpu1.op_class::IntMult 271069 0.21% 69.57% # Class of executed instruction
system.cpu1.op_class::IntDiv 11362 0.01% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 11625 0.01% 69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction
system.cpu1.op_class::MemRead 20434165 15.97% 85.56% # Class of executed instruction
system.cpu1.op_class::MemWrite 18471025 14.44% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 127939763 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 40521416 # Number of BP lookups
system.cpu2.branchPred.condPredicted 28118087 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 2031475 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 29676837 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 20868777 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 70.320085 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 4994532 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 335745 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.walker.walks 95252 # Table walker walks requested
system.cpu2.dtb.walker.walksLong 95252 # Table walker walks initiated with long descriptors
system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7000 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29929 # Level at which table walker walks with long descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 95252 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 95252 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 95252 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 36929 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 24871.388340 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 22228.503196 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 11289.834647 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::0-32767 23698 64.17% 64.17% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::32768-65535 13086 35.44% 99.61% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::65536-98303 84 0.23% 99.83% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::98304-131071 38 0.10% 99.94% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::163840-196607 9 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 36929 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000228500 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000228500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000228500 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 29929 81.04% 81.04% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::2M 7000 18.96% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 36929 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 95252 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 95252 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36929 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36929 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 132181 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 29009718 # DTB read hits
system.cpu2.dtb.read_misses 79511 # DTB read misses
system.cpu2.dtb.write_hits 25340544 # DTB write hits
system.cpu2.dtb.write_misses 15741 # DTB write misses
system.cpu2.dtb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 6565 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 192 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 22319 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 74 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 2265 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 3693 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 29089229 # DTB read accesses
system.cpu2.dtb.write_accesses 25356285 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 54350262 # DTB hits
system.cpu2.dtb.misses 95252 # DTB misses
system.cpu2.dtb.accesses 54445514 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.itb.walker.walks 27224 # Table walker walks requested
system.cpu2.itb.walker.walksLong 27224 # Table walker walks initiated with long descriptors
system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1814 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22841 # Level at which table walker walks with long descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 27224 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 27224 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 27224 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 24655 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 27863.922125 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 25521.619222 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 11746.072802 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::0-32767 11779 47.78% 47.78% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::32768-65535 12711 51.56% 99.33% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::65536-98303 67 0.27% 99.60% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::98304-131071 84 0.34% 99.94% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::131072-163839 1 0.00% 99.95% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::163840-196607 5 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 24655 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000202500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000202500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000202500 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 22841 92.64% 92.64% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::2M 1814 7.36% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 24655 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27224 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27224 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24655 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24655 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 51879 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 69987684 # ITB inst hits
system.cpu2.itb.inst_misses 27224 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 6565 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 192 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 17001 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 55845 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 70014908 # ITB inst accesses
system.cpu2.itb.hits 69987684 # DTB hits
system.cpu2.itb.misses 27224 # DTB misses
system.cpu2.itb.accesses 70014908 # DTB accesses
system.cpu2.numCycles 6727315780 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.committedInsts 148611673 # Number of instructions committed
system.cpu2.committedOps 174373358 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 14098587 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 1631 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 95904949193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 45.267748 # CPI: cycles per instruction
system.cpu2.ipc 0.022091 # IPC: instructions per cycle
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.tickCycles 276122031 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 6451193749 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 75051711 # Number of BP lookups
system.cpu3.branchPred.condPredicted 50745018 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 3426540 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 51416576 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 36523401 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct 71.034293 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 9845099 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 104872 # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu3.dtb.walker.walks 518940 # Table walker walks requested
system.cpu3.dtb.walker.walksLong 518940 # Table walker walks initiated with long descriptors
system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8603 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 51054 # Level at which table walker walks with long descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 322381 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 196559 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 2153.353446 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 12453.010606 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-65535 195431 99.43% 99.43% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-131071 797 0.41% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-196607 204 0.10% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::196608-262143 65 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::262144-327679 34 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::327680-393215 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total 196559 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 238895 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 21937.397183 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 18018.053356 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.644026 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-32767 188060 78.72% 78.72% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::32768-65535 46353 19.40% 98.12% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3667 1.53% 99.66% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::98304-131071 466 0.20% 99.85% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.88% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::163840-196607 89 0.04% 99.92% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::196608-229375 102 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::229376-262143 32 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::262144-294911 22 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::294912-327679 17 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::327680-360447 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 238895 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -25404728884 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean 1.186676 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-3 -25965813384 102.21% 102.21% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-7 315763500 -1.24% 100.97% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-11 105079500 -0.41% 100.55% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-15 65519000 -0.26% 100.29% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-19 25638000 -0.10% 100.19% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-23 14396000 -0.06% 100.14% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-27 12378500 -0.05% 100.09% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-31 18510000 -0.07% 100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::32-35 3399500 -0.01% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::36-39 261000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::40-43 34500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::44-47 99500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::48-51 5500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -25404728884 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 51054 85.58% 85.58% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::2M 8603 14.42% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 59657 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 518940 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 518940 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59657 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59657 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 578597 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
system.cpu3.dtb.read_hits 58887686 # DTB read hits
system.cpu3.dtb.read_misses 354452 # DTB read misses
system.cpu3.dtb.write_hits 46401949 # DTB write hits
system.cpu3.dtb.write_misses 164488 # DTB write misses
system.cpu3.dtb.flush_tlb 1183 # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid 11695 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 298 # Number of times TLB was flushed by ASID
system.cpu3.dtb.flush_entries 29305 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 5086 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dtb.perms_faults 31208 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 59242138 # DTB read accesses
system.cpu3.dtb.write_accesses 46566437 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
system.cpu3.dtb.hits 105289635 # DTB hits
system.cpu3.dtb.misses 518940 # DTB misses
system.cpu3.dtb.accesses 105808575 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu3.itb.walker.walks 61371 # Table walker walks requested
system.cpu3.itb.walker.walksLong 61371 # Table walker walks initiated with long descriptors
system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1880 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41824 # Level at which table walker walks with long descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 8320 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 53051 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1484.693974 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 7949.697617 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-32767 52591 99.13% 99.13% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-65535 303 0.57% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-98303 95 0.18% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::98304-131071 39 0.07% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::131072-163839 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::163840-196607 10 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::229376-262143 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 53051 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 52024 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 27951.877979 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 24094.893737 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 16939.258391 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-65535 51107 98.24% 98.24% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::65536-131071 782 1.50% 99.74% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::131072-196607 83 0.16% 99.90% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.95% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::327680-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 52024 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -25407358384 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 1.082792 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 2146509568 -8.45% -8.45% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -27591517452 108.60% 100.15% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 32946500 -0.13% 100.02% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 4144000 -0.02% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 483500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5 75500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -25407358384 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 41824 95.70% 95.70% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::2M 1880 4.30% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 43704 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 61371 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 61371 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43704 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43704 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 105075 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 54222751 # ITB inst hits
system.cpu3.itb.inst_misses 61371 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
system.cpu3.itb.flush_tlb 1183 # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid 11695 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 298 # Number of times TLB was flushed by ASID
system.cpu3.itb.flush_entries 22112 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.itb.perms_faults 119556 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
system.cpu3.itb.inst_accesses 54284122 # ITB inst accesses
system.cpu3.itb.hits 54222751 # DTB hits
system.cpu3.itb.misses 61371 # DTB misses
system.cpu3.itb.accesses 54284122 # DTB accesses
system.cpu3.numCycles 362116242 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles 140692068 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 333606704 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 75051711 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 46368500 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 200357205 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 7729147 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 1466432 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 2417 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 3039056 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 93220 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 3908 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 54085330 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 2111003 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 24755 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 349524457 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.117326 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.359483 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0 267214314 76.45% 76.45% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 10401691 2.98% 79.43% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 10376538 2.97% 82.40% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 7732436 2.21% 84.61% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 15785532 4.52% 89.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 5057577 1.45% 90.57% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 5498876 1.57% 92.14% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 4902371 1.40% 93.55% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 22555122 6.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total 349524457 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.207259 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.921270 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 115102148 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 163151118 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 60941298 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 7267408 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 3060603 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 11237446 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 815602 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 364546839 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 2510722 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 3060603 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 119327697 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 12479500 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 131448496 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 63890938 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 19315280 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 355739076 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 49184 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 1032074 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 774475 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 9071524 # Number of times rename has blocked due to SQ full
system.cpu3.rename.FullRegisterEvents 2005 # Number of times there has been no free registers
system.cpu3.rename.RenamedOperands 339501197 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 543916726 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 420235861 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 502563 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 283815673 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 55685519 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 8092119 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 6958081 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 40275448 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 57221877 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 48841814 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 7500676 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 8056084 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 337690712 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 8109511 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 336678168 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 492039 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 46643392 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 29867606 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 195066 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 349524457 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.963246 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.677033 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0 218668838 62.56% 62.56% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 53919118 15.43% 77.99% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 24783168 7.09% 85.08% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 17648409 5.05% 90.13% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 13036700 3.73% 93.86% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 9178789 2.63% 96.48% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 6241479 1.79% 98.27% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 3625780 1.04% 99.31% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 2422176 0.69% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total 349524457 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu 1699142 25.95% 25.95% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 17812 0.27% 26.22% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 1053 0.02% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.24% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 2601719 39.74% 65.97% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 2227949 34.03% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 228602725 67.90% 67.90% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 820222 0.24% 68.14% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 38384 0.01% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 5 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 43257 0.01% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 60130906 17.86% 86.03% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 47042657 13.97% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total 336678168 # Type of FU issued
system.cpu3.iq.rate 0.929752 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 6547675 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.019448 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 1029252740 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 392488113 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 324616709 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 667767 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 333618 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 297362 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 342868261 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 357570 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 2662931 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads 9411324 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 12714 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 384094 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 5127738 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 2090075 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 3953629 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles 3060603 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 8381523 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 3212246 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 345878827 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 1059491 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 57221877 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 48841814 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 6807675 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 123383 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 3041851 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 384094 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 1583894 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 1359451 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 2943345 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 332673161 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 58878878 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 3493066 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
system.cpu3.iew.exec_nop 78604 # number of nop insts executed
system.cpu3.iew.exec_refs 105279838 # number of memory reference insts executed
system.cpu3.iew.exec_branches 61795726 # Number of branches executed
system.cpu3.iew.exec_stores 46400960 # Number of stores executed
system.cpu3.iew.exec_rate 0.918692 # Inst execution rate
system.cpu3.iew.wb_sent 325632326 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 324914071 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 160314385 # num instructions producing a value
system.cpu3.iew.wb_consumers 278113551 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate 0.897265 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.576435 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts 46667653 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7914445 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 2622372 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 341617018 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.875708 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.868271 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0 232826047 68.15% 68.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 52669534 15.42% 83.57% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 19043564 5.57% 89.15% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 8581535 2.51% 91.66% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 6262304 1.83% 93.49% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 3681580 1.08% 94.57% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 3506851 1.03% 95.60% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 2207487 0.65% 96.24% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 12838116 3.76% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 341617018 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 254540187 # Number of instructions committed
system.cpu3.commit.committedOps 299156826 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 91524628 # Number of memory references committed
system.cpu3.commit.loads 47810552 # Number of loads committed
system.cpu3.commit.membars 2044329 # Number of memory barriers committed
system.cpu3.commit.branches 56838517 # Number of branches committed
system.cpu3.commit.fp_insts 284474 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 274963169 # Number of committed integer instructions.
system.cpu3.commit.function_calls 7559690 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu 206931641 69.17% 69.17% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 635252 0.21% 69.38% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 28375 0.01% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 36930 0.01% 69.41% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.41% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.41% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.41% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 47810552 15.98% 85.39% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 43714076 14.61% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total 299156826 # Class of committed instruction
system.cpu3.commit.bw_lim_events 12838116 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 672513030 # The number of ROB reads
system.cpu3.rob.rob_writes 699568614 # The number of ROB writes
system.cpu3.timesIdled 2366771 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 12591785 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 98718850803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 254540187 # Number of Instructions Simulated
system.cpu3.committedOps 299156826 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.422629 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.422629 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.702924 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.702924 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 392099204 # number of integer regfile reads
system.cpu3.int_regfile_writes 232294349 # number of integer regfile writes
system.cpu3.fp_regfile_reads 578128 # number of floating regfile reads
system.cpu3.fp_regfile_writes 349384 # number of floating regfile writes
system.cpu3.cc_regfile_reads 70503993 # number of cc regfile reads
system.cpu3.cc_regfile_writes 71192448 # number of cc regfile writes
system.cpu3.misc_regfile_reads 655577760 # number of misc regfile reads
system.cpu3.misc_regfile_writes 7960975 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40269 # Transaction distribution
system.iobus.trans_dist::ReadResp 40269 # Transaction distribution
system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353616 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 14862000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 10142000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 45000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 18725000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 244315631 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 45003000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 69196000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115462 # number of replacements
system.iocache.tags.tagsinuse 10.425339 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13087689855509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544644 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.880695 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.430043 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651584 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039677 # Number of tag accesses
system.iocache.tags.data_accesses 1039677 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses
system.iocache.demand_misses::total 8856 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8816 # number of overall misses
system.iocache.overall_misses::total 8856 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 902834218 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 902834218 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 5365256413 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 5365256413 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 902834218 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 902834218 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 902834218 # number of overall miss cycles
system.iocache.overall_miss_latency::total 902834218 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 102408.600045 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 101980.596182 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 50300.536385 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 50300.536385 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 102408.600045 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 101946.049910 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 102408.600045 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 101946.049910 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 17834 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 1976 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.025304 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 4982 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 4982 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 45408 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 45408 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 4982 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 4982 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 4982 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 4982 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 653734218 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 653734218 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3094856413 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 3094856413 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 653734218 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 653734218 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 653734218 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 653734218 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.562747 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.425711 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.425711 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.562556 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.562556 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131219.232838 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 131219.232838 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68156.633479 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68156.633479 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 131219.232838 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 131219.232838 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 131219.232838 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 131219.232838 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1197494 # number of replacements
system.l2c.tags.tagsinuse 65334.177646 # Cycle average of tags in use
system.l2c.tags.total_refs 47583797 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1260356 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 37.754251 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36625.887647 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 129.652823 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 192.600178 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3297.722493 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 10271.458508 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.360816 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 62.862423 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 734.403230 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2295.121948 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.166542 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.itb.walker 55.564036 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2274.574548 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3138.217003 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 98.389522 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.itb.walker 140.202266 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 1940.354614 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 3994.639050 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.558867 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001978 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.002939 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.050319 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.156730 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000959 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.011206 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.035021 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000582 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000848 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.034707 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.047885 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001501 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.itb.walker 0.002139 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.029607 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.060953 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996920 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 305 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62557 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 569 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2827 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5128 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 53917 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004654 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.954544 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 421629401 # Number of tag accesses
system.l2c.tags.data_accesses 421629401 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 162534 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 110569 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 55382 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 41930 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 157494 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 59360 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 299154 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 112124 # number of ReadReq hits
system.l2c.ReadReq_hits::total 998547 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 7530303 # number of Writeback hits
system.l2c.Writeback_hits::total 7530303 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3865 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1247 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 1535 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 2775 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 9422 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 2 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 634082 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 192446 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 277703 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 471607 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1575838 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 5493197 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 1685224 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 3887506 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 4647283 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15713210 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 2580953 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 758591 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 1060227 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 1868057 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6267828 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 284671 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 86494 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu2.data 126322 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu3.data 229482 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 726969 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 162534 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 110569 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 5493197 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 3215035 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 55382 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 41930 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 1685224 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 951037 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 157494 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 59360 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 3887506 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 1337930 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 299154 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 112124 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 4647283 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 2339664 # number of demand (read+write) hits
system.l2c.demand_hits::total 24555423 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 162534 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 110569 # number of overall hits
system.l2c.overall_hits::cpu0.inst 5493197 # number of overall hits
system.l2c.overall_hits::cpu0.data 3215035 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 55382 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 41930 # number of overall hits
system.l2c.overall_hits::cpu1.inst 1685224 # number of overall hits
system.l2c.overall_hits::cpu1.data 951037 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 157494 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 59360 # number of overall hits
system.l2c.overall_hits::cpu2.inst 3887506 # number of overall hits
system.l2c.overall_hits::cpu2.data 1337930 # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker 299154 # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker 112124 # number of overall hits
system.l2c.overall_hits::cpu3.inst 4647283 # number of overall hits
system.l2c.overall_hits::cpu3.data 2339664 # number of overall hits
system.l2c.overall_hits::total 24555423 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1348 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1360 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 417 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 408 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 426 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 363 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker 1018 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.itb.walker 932 # number of ReadReq misses
system.l2c.ReadReq_misses::total 6272 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 14062 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 4585 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 5739 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 9908 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 34294 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 188559 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 51076 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 66860 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 112125 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 418620 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 35995 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 10966 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 27651 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 28085 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 102697 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 119057 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 33042 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 40134 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 73982 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 266215 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 383686 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 19000 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu2.data 28887 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu3.data 66669 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 498242 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1348 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1360 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 35995 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 307616 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 417 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 408 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 10966 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 84118 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 426 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 363 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 27651 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 106994 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker 1018 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.itb.walker 932 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 28085 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 186107 # number of demand (read+write) misses
system.l2c.demand_misses::total 793804 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1348 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1360 # number of overall misses
system.l2c.overall_misses::cpu0.inst 35995 # number of overall misses
system.l2c.overall_misses::cpu0.data 307616 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 417 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 408 # number of overall misses
system.l2c.overall_misses::cpu1.inst 10966 # number of overall misses
system.l2c.overall_misses::cpu1.data 84118 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 426 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 363 # number of overall misses
system.l2c.overall_misses::cpu2.inst 27651 # number of overall misses
system.l2c.overall_misses::cpu2.data 106994 # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker 1018 # number of overall misses
system.l2c.overall_misses::cpu3.itb.walker 932 # number of overall misses
system.l2c.overall_misses::cpu3.inst 28085 # number of overall misses
system.l2c.overall_misses::cpu3.data 186107 # number of overall misses
system.l2c.overall_misses::total 793804 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 35190000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 35160000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 36174500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.itb.walker 31569500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 89352000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.itb.walker 82579500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 310025500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 68776500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 92773000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data 156127500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 317677000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data 81000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 81000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4115650000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 5398260500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 10994713000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 20508623500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 887226500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2301476500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2388363000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 5577066000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 2751846000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data 3344905000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data 6580498500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 12677249500 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 1513300000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu2.data 2542083000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu3.data 7155981000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 11211364000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 35190000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 35160000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 887226500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 6867496000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 36174500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.itb.walker 31569500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 2301476500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 8743165500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker 89352000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.itb.walker 82579500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 2388363000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 17575211500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 39072964500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 35190000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 35160000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 887226500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 6867496000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 36174500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.itb.walker 31569500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 2301476500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 8743165500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker 89352000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.itb.walker 82579500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 2388363000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 17575211500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 39072964500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 163882 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 111929 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 55799 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 42338 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 157920 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 59723 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker 300172 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker 113056 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1004819 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 7530303 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 7530303 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 17927 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 5832 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::cpu3.data 12683 # number of UpgradeReq accesses(hits+misses)
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system.l2c.ReadCleanReq_miss_rate::total 0.006493 # miss rate for ReadCleanReq accesses
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system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007473 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009637 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002698 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.006078 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003361 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008146 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.003527 # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.788974 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.781203 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.462805 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.194043 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.192083 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.115350 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006465 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.007063 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.006007 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.004217 # mshr miss rate for ReadCleanReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.036471 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.038093 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.022521 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.180105 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.186117 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.225118 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.093499 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007473 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009637 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006465 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.081261 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002698 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.006078 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007063 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.074046 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003361 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008146 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006007 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009637 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006465 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002698 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.006078 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.007063 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.074046 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003361 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008146 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006007 # mshr miss rate for overall accesses
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588 # average ReadReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295 # average ReadReq mshr miss latency
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system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20750 # average UpgradeReq mshr miss latency
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system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45750 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45750 # average SCUpgradeReq mshr miss latency
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system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88057.641026 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 79144.285646 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70907.030823 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73233.029547 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75043.138442 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73612.756930 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73283.275831 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73345.892203 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78948.316414 # average ReadSharedReq mshr miss latency
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system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69647.368421 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78000.934676 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97335.958241 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 87867.977234 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70907.030823 # average overall mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73233.029547 # average overall mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75043.138442 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84436.554292 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70907.030823 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71641.218289 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73233.029547 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71717.289305 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75043.138442 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84436.554292 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 77318.672367 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163713.586098 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 156199.733005 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161400.414938 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160733.722455 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168691.861472 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 157871.958153 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169235.221950 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165611.736609 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166088.599752 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156993.254910 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165175.910996 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 163064.272674 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 76739 # Transaction distribution
system.membus.trans_dist::ReadResp 460749 # Transaction distribution
system.membus.trans_dist::WriteReq 33648 # Transaction distribution
system.membus.trans_dist::WriteResp 33648 # Transaction distribution
system.membus.trans_dist::Writeback 1098433 # Transaction distribution
system.membus.trans_dist::CleanEvict 213962 # Transaction distribution
system.membus.trans_dist::UpgradeReq 34949 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 34951 # Transaction distribution
system.membus.trans_dist::ReadExReq 916210 # Transaction distribution
system.membus.trans_dist::ReadExResp 916210 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 384010 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 62 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6762 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3942227 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4071627 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343658 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 343658 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4415285 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13524 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146305120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 146474546 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302336 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7302336 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 153776882 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1554 # Total snoops (count)
system.membus.snoop_fanout::samples 2866082 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 2866082 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2866082 # Request fanout histogram
system.membus.reqLayer0.occupancy 51617000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1694500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 3281296074 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 3058096264 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 103726218 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 1507075 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 23857599 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 8015609 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 18152591 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 43716 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 43720 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 1994458 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 1994458 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 15815989 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 6539025 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1270619 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1225211 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47531663 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29482635 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 826355 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1753245 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 79593898 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1012390548 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1027984926 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2989368 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6204744 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2049569586 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 999459 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 53440188 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.040190 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.196406 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 51292404 95.98% 95.98% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 2147784 4.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 53440188 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 20656393480 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 15434172491 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 7824329236 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 294252739 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 716654510 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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