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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.841548 # Number of seconds simulated
sim_ticks 1841548033500 # Number of ticks simulated
final_tick 1841548033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 218310 # Simulator instruction rate (inst/s)
host_op_rate 218310 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5702515722 # Simulator tick rate (ticks/s)
host_mem_usage 375536 # Number of bytes of host memory used
host_seconds 322.94 # Real time elapsed on the host
sim_insts 70500110 # Number of instructions simulated
sim_ops 70500110 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 465600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 20057408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 147136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 2156416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 307456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 2656704 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 465600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 147136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 307456 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 920192 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7484672 # Number of bytes written to this memory
system.physmem.bytes_written::total 7484672 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 7275 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 313397 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 33694 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4804 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 41511 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 116948 # Number of write requests responded to by this memory
system.physmem.num_writes::total 116948 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 252831 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 10891602 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 79898 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1170980 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 166955 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 1442647 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 14005434 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 252831 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 79898 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 166955 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 499684 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 4064337 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 4064337 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 4064337 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 252831 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 10891602 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 79898 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1170980 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 166955 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1442647 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 18069771 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 82323 # Number of read requests accepted
system.physmem.writeReqs 47461 # Number of write requests accepted
system.physmem.readBursts 82323 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 47461 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5267264 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue
system.physmem.bytesWritten 3035584 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5268672 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 3037504 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 17348 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 4998 # Per bank write bursts
system.physmem.perBankRdBursts::1 5047 # Per bank write bursts
system.physmem.perBankRdBursts::2 4951 # Per bank write bursts
system.physmem.perBankRdBursts::3 4902 # Per bank write bursts
system.physmem.perBankRdBursts::4 5135 # Per bank write bursts
system.physmem.perBankRdBursts::5 5137 # Per bank write bursts
system.physmem.perBankRdBursts::6 5321 # Per bank write bursts
system.physmem.perBankRdBursts::7 5238 # Per bank write bursts
system.physmem.perBankRdBursts::8 5355 # Per bank write bursts
system.physmem.perBankRdBursts::9 4827 # Per bank write bursts
system.physmem.perBankRdBursts::10 5539 # Per bank write bursts
system.physmem.perBankRdBursts::11 5124 # Per bank write bursts
system.physmem.perBankRdBursts::12 4881 # Per bank write bursts
system.physmem.perBankRdBursts::13 5044 # Per bank write bursts
system.physmem.perBankRdBursts::14 5631 # Per bank write bursts
system.physmem.perBankRdBursts::15 5171 # Per bank write bursts
system.physmem.perBankWrBursts::0 2712 # Per bank write bursts
system.physmem.perBankWrBursts::1 2869 # Per bank write bursts
system.physmem.perBankWrBursts::2 2967 # Per bank write bursts
system.physmem.perBankWrBursts::3 2927 # Per bank write bursts
system.physmem.perBankWrBursts::4 2992 # Per bank write bursts
system.physmem.perBankWrBursts::5 2769 # Per bank write bursts
system.physmem.perBankWrBursts::6 3293 # Per bank write bursts
system.physmem.perBankWrBursts::7 2918 # Per bank write bursts
system.physmem.perBankWrBursts::8 3398 # Per bank write bursts
system.physmem.perBankWrBursts::9 2634 # Per bank write bursts
system.physmem.perBankWrBursts::10 3325 # Per bank write bursts
system.physmem.perBankWrBursts::11 2913 # Per bank write bursts
system.physmem.perBankWrBursts::12 2642 # Per bank write bursts
system.physmem.perBankWrBursts::13 2800 # Per bank write bursts
system.physmem.perBankWrBursts::14 3388 # Per bank write bursts
system.physmem.perBankWrBursts::15 2884 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
system.physmem.totGap 1840536161000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 82323 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 47461 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 64278 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 7820 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5619 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2418 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3843 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 3517 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 2960 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 3353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 2671 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 2656 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 3003 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 2408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 2268 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 2164 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 88 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 21805 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 380.777253 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 217.097266 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 378.211296 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 7203 33.03% 33.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 4880 22.38% 55.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 2010 9.22% 64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1038 4.76% 69.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 857 3.93% 73.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 538 2.47% 75.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 425 1.95% 77.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 372 1.71% 79.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4482 20.55% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 21805 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 2075 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 39.654458 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 980.113813 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 2073 99.90% 99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 2075 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 2075 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.858313 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.353134 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 24.870235 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 34 1.64% 1.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 7 0.34% 1.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 2 0.10% 2.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 5 0.24% 2.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 1736 83.66% 85.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 36 1.73% 87.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 80 3.86% 91.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 17 0.82% 92.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 12 0.58% 92.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 17 0.82% 93.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 5 0.24% 94.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 1 0.05% 94.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 1 0.05% 94.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 2 0.10% 94.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 3 0.14% 94.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 1 0.05% 94.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.19% 94.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 1 0.05% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 2 0.10% 94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.05% 94.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.14% 94.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 9 0.43% 95.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 4 0.19% 95.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 65 3.13% 98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 3 0.14% 98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 3 0.14% 98.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.05% 99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 2 0.10% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.05% 99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.05% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.05% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183 2 0.10% 99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187 2 0.10% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 2 0.10% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219 1 0.05% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::220-223 3 0.14% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-227 1 0.05% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::228-231 4 0.19% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 2075 # Writes before turning the bus around for reads
system.physmem.totQLat 914891250 # Total ticks spent queuing
system.physmem.totMemAccLat 2458035000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 411505000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11116.41 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 29866.41 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 2.86 # Average write queue length when enqueuing
system.physmem.readRowHits 70476 # Number of row buffer hits during reads
system.physmem.writeRowHits 37451 # Number of row buffer hits during writes
system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.91 # Row buffer hit rate for writes
system.physmem.avgGap 14181533.63 # Average gap between requests
system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 81194400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 44195250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 317686200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 151936560 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 35637705585 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 799850646000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 925140356955 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.881529 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1309035077000 # Time in different power states
system.physmem_0.memoryStateTime::REF 45530160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 9110965500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 83651400 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 45474000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 324261600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 155416320 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 35441943930 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 803933138250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 929040878460 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.556246 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1309294919000 # Time in different power states
system.physmem_1.memoryStateTime::REF 45530160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 8868165750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 4775602 # DTB read hits
system.cpu0.dtb.read_misses 5966 # DTB read misses
system.cpu0.dtb.read_acv 109 # DTB read access violations
system.cpu0.dtb.read_accesses 428378 # DTB read accesses
system.cpu0.dtb.write_hits 3387346 # DTB write hits
system.cpu0.dtb.write_misses 667 # DTB write misses
system.cpu0.dtb.write_acv 80 # DTB write access violations
system.cpu0.dtb.write_accesses 163776 # DTB write accesses
system.cpu0.dtb.data_hits 8162948 # DTB hits
system.cpu0.dtb.data_misses 6633 # DTB misses
system.cpu0.dtb.data_acv 189 # DTB access violations
system.cpu0.dtb.data_accesses 592154 # DTB accesses
system.cpu0.itb.fetch_hits 2717036 # ITB hits
system.cpu0.itb.fetch_misses 3019 # ITB misses
system.cpu0.itb.fetch_acv 97 # ITB acv
system.cpu0.itb.fetch_accesses 2720055 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 930055234 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 31475732 # Number of instructions committed
system.cpu0.committedOps 31475732 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 29412106 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 162586 # Number of float alu accesses
system.cpu0.num_func_calls 792411 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4104277 # number of instructions that are conditional controls
system.cpu0.num_int_insts 29412106 # number of integer instructions
system.cpu0.num_fp_insts 162586 # number of float instructions
system.cpu0.num_int_register_reads 40967178 # number of times the integer registers were read
system.cpu0.num_int_register_writes 21562005 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 84110 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 85570 # number of times the floating registers were written
system.cpu0.num_mem_refs 8192042 # number of memory refs
system.cpu0.num_load_insts 4796241 # Number of load instructions
system.cpu0.num_store_insts 3395801 # Number of store instructions
system.cpu0.num_idle_cycles 907058327.289346 # Number of idle cycles
system.cpu0.num_busy_cycles 22996906.710654 # Number of busy cycles
system.cpu0.not_idle_fraction 0.024726 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.975274 # Percentage of idle cycles
system.cpu0.Branches 5151040 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1559860 4.95% 4.95% # Class of executed instruction
system.cpu0.op_class::IntAlu 21040910 66.83% 71.79% # Class of executed instruction
system.cpu0.op_class::IntMult 31347 0.10% 71.89% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 71.89% # Class of executed instruction
system.cpu0.op_class::FloatAdd 12827 0.04% 71.93% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::FloatDiv 1598 0.01% 71.93% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.93% # Class of executed instruction
system.cpu0.op_class::MemRead 4926196 15.65% 87.58% # Class of executed instruction
system.cpu0.op_class::MemWrite 3398883 10.80% 98.38% # Class of executed instruction
system.cpu0.op_class::IprAccess 510933 1.62% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 31482554 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 211358 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1818800243000 98.76% 98.76% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 38808500 0.00% 98.77% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 357216000 0.02% 98.79% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 22351032000 1.21% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1841547299500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 326 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 192209 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1906
system.cpu0.kern.mode_good::user 1737
system.cpu0.kern.mode_good::idle 169
system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 29750547000 1.62% 1.62% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 2575384000 0.14% 1.76% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1809221366500 98.24% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.cpu0.dcache.tags.replacements 1393348 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 13255372 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1393860 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.509830 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.816582 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.221248 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.959986 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.347298 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.320745 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.331953 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63362265 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63362265 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 3956098 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1080024 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 2536463 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 7572585 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3101293 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 830391 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 1367001 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 5298685 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113681 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19703 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51298 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 184682 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122268 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21809 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55240 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 7057391 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 1910415 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 3903464 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 12871270 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 7057391 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 1910415 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 3903464 # number of overall hits
system.cpu0.dcache.overall_hits::total 12871270 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 706776 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 97332 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 562527 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1366635 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 162364 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 44132 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 644654 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 851150 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9134 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2235 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7668 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 19037 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 10 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 869140 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 141464 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 1207181 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2217785 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 869140 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 141464 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1207181 # number of overall misses
system.cpu0.dcache.overall_misses::total 2217785 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2268250000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8231829500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 10500079500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1752940000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19634310548 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 21387250548 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29559000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 124972000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 154531000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 170500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 170500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 4021190000 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 27866140048 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 31887330048 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 4021190000 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 27866140048 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 31887330048 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 4662874 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1177356 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 3098990 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8939220 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3263657 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 874523 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2011655 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 6149835 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122815 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21938 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58966 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 203719 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122268 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21809 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55250 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199327 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 7926531 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2051879 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 5110645 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 15089055 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 7926531 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2051879 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 5110645 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 15089055 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151575 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082670 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181519 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.152881 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049749 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050464 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.320460 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.138402 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.074372 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101878 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130041 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093447 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000181 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000050 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109649 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068944 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.236209 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.146980 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109649 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068944 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.236209 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.146980 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23304.257593 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14633.661140 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.163025 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39720.384302 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30457.129791 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 25127.475237 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13225.503356 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16297.861242 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8117.402952 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 17050 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17050 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14378.007809 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 14378.007809 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 1019885 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1764 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 60259 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 18 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.925024 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 98 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 835740 # number of writebacks
system.cpu0.dcache.writebacks::total 835740 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292598 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 292598 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548626 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 548626 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1690 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1690 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 841224 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 841224 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 841224 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 841224 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97332 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269929 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 367261 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44132 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 96028 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 140160 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2235 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5978 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8213 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 10 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 141464 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 365957 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 507421 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 141464 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 365957 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 507421 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1108 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1559 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2667 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1387 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3515 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2495 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3687 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6182 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170918000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4426676000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6597594000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1708808000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3106661815 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4815469815 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 27324000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 74701500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102025500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 160500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3879726000 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7533337815 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 11413063815 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3879726000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7533337815 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 11413063815 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226454500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334463500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560918000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298425500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450956500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749382000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524880000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785420000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1310300000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082670 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087102 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041084 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050464 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047736 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022791 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101878 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101380 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040315 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000181 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000050 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.033628 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.033628 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22304.257593 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16399.408733 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17964.319653 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38720.384302 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32351.624682 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34356.947881 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12225.503356 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12496.068919 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.440034 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16050 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16050 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204381.317690 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214537.203335 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210317.960255 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215158.976208 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211915.648496 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.448080 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210372.745491 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213024.138866 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211954.060175 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 965393 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.914113 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 41264625 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 965904 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 42.721249 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10188445500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.904249 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 135.394605 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 228.615259 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286922 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.264443 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.446514 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997879 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 43213951 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 43213951 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 30975792 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 7803098 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 2485735 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 41264625 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 30975792 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 7803098 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 2485735 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 41264625 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 30975792 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 7803098 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 2485735 # number of overall hits
system.cpu0.icache.overall_hits::total 41264625 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 506762 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 129019 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 347436 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 983217 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 506762 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 129019 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 347436 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 983217 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 506762 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 129019 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 347436 # number of overall misses
system.cpu0.icache.overall_misses::total 983217 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1839982500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4838575988 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 6678558488 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1839982500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4838575988 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 6678558488 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1839982500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4838575988 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 6678558488 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 31482554 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 7932117 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 2833171 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 42247842 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 31482554 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 7932117 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 2833171 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 42247842 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 31482554 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 7932117 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 2833171 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 42247842 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016097 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016265 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122631 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.023273 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016097 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016265 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122631 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.023273 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016097 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016265 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122631 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.023273 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14261.329727 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13926.524563 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6792.557989 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13926.524563 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6792.557989 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13926.524563 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6792.557989 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 3935 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 210 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.738095 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 17108 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 17108 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 17108 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 17108 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 17108 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 17108 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129019 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 330328 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 459347 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 129019 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 330328 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 459347 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 129019 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 330328 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 459347 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1710963500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4315526491 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 6026489991 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1710963500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4315526491 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 6026489991 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1710963500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4315526491 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 6026489991 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010873 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.010873 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.010873 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13119.689453 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 1196955 # DTB read hits
system.cpu1.dtb.read_misses 1325 # DTB read misses
system.cpu1.dtb.read_acv 35 # DTB read access violations
system.cpu1.dtb.read_accesses 141268 # DTB read accesses
system.cpu1.dtb.write_hits 896481 # DTB write hits
system.cpu1.dtb.write_misses 169 # DTB write misses
system.cpu1.dtb.write_acv 22 # DTB write access violations
system.cpu1.dtb.write_accesses 57742 # DTB write accesses
system.cpu1.dtb.data_hits 2093436 # DTB hits
system.cpu1.dtb.data_misses 1494 # DTB misses
system.cpu1.dtb.data_acv 57 # DTB access violations
system.cpu1.dtb.data_accesses 199010 # DTB accesses
system.cpu1.itb.fetch_hits 858438 # ITB hits
system.cpu1.itb.fetch_misses 659 # ITB misses
system.cpu1.itb.fetch_acv 35 # ITB acv
system.cpu1.itb.fetch_accesses 859097 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 953273349 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 7930565 # Number of instructions committed
system.cpu1.committedOps 7930565 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 7389333 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 45920 # Number of float alu accesses
system.cpu1.num_func_calls 207460 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1022605 # number of instructions that are conditional controls
system.cpu1.num_int_insts 7389333 # number of integer instructions
system.cpu1.num_fp_insts 45920 # number of float instructions
system.cpu1.num_int_register_reads 10362144 # number of times the integer registers were read
system.cpu1.num_int_register_writes 5369975 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24736 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written
system.cpu1.num_mem_refs 2100568 # number of memory refs
system.cpu1.num_load_insts 1201762 # Number of load instructions
system.cpu1.num_store_insts 898806 # Number of store instructions
system.cpu1.num_idle_cycles 922154358.750069 # Number of idle cycles
system.cpu1.num_busy_cycles 31118990.249931 # Number of busy cycles
system.cpu1.not_idle_fraction 0.032644 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.967356 # Percentage of idle cycles
system.cpu1.Branches 1296677 # Number of branches fetched
system.cpu1.op_class::No_OpClass 410840 5.18% 5.18% # Class of executed instruction
system.cpu1.op_class::IntAlu 5240708 66.07% 71.25% # Class of executed instruction
system.cpu1.op_class::IntMult 8731 0.11% 71.36% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 71.36% # Class of executed instruction
system.cpu1.op_class::FloatAdd 5176 0.07% 71.42% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 71.42% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 71.42% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 71.42% # Class of executed instruction
system.cpu1.op_class::FloatDiv 810 0.01% 71.43% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.43% # Class of executed instruction
system.cpu1.op_class::MemRead 1230901 15.52% 86.95% # Class of executed instruction
system.cpu1.op_class::MemWrite 900034 11.35% 98.30% # Class of executed instruction
system.cpu1.op_class::IprAccess 134916 1.70% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 7932116 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu1.kern.mode_switch::user 0 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 0
system.cpu1.kern.mode_good::user 0
system.cpu1.kern.mode_good::idle 0
system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
system.cpu2.branchPred.lookups 10402334 # Number of BP lookups
system.cpu2.branchPred.condPredicted 9657881 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 126933 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 8330137 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 6272162 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 75.294824 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 302639 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 7723 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
system.cpu2.dtb.read_hits 3549115 # DTB read hits
system.cpu2.dtb.read_misses 12776 # DTB read misses
system.cpu2.dtb.read_acv 157 # DTB read access violations
system.cpu2.dtb.read_accesses 225358 # DTB read accesses
system.cpu2.dtb.write_hits 2157791 # DTB write hits
system.cpu2.dtb.write_misses 2831 # DTB write misses
system.cpu2.dtb.write_acv 142 # DTB write access violations
system.cpu2.dtb.write_accesses 84650 # DTB write accesses
system.cpu2.dtb.data_hits 5706906 # DTB hits
system.cpu2.dtb.data_misses 15607 # DTB misses
system.cpu2.dtb.data_acv 299 # DTB access violations
system.cpu2.dtb.data_accesses 310008 # DTB accesses
system.cpu2.itb.fetch_hits 538598 # ITB hits
system.cpu2.itb.fetch_misses 5991 # ITB misses
system.cpu2.itb.fetch_acv 159 # ITB acv
system.cpu2.itb.fetch_accesses 544589 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.write_acv 0 # DTB write access violations
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
system.cpu2.numCycles 30759536 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 9338114 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 39735788 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 10402334 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 6574801 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 19282744 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 413720 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 277 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 9678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1944 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 234903 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 108900 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 473 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 2833173 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 93993 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 29183655 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.361577 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.367035 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 20063773 68.75% 68.75% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 307542 1.05% 69.80% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 477296 1.64% 71.44% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 4654234 15.95% 87.39% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 859104 2.94% 90.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 198525 0.68% 91.01% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 235442 0.81% 91.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 432653 1.48% 93.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 1955086 6.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 29183655 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.338182 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.291820 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 7672062 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 13049396 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 7739525 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 528158 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 193789 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 177139 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 13443 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36353966 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 42512 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 193789 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 7950274 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 4574250 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 6325048 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 7961138 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 2178432 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 35523870 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 60190 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 394243 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 57916 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 1115509 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 23763436 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 44289897 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 44229633 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 56339 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 21842362 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 1921074 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 535035 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 63809 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3839801 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3528507 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 2250963 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 468940 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 330687 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 32977065 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 683079 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 32678030 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 15337 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 2566331 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 1147551 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 488786 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 29183655 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.119737 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.624192 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 17436459 59.75% 59.75% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 2753806 9.44% 69.18% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 1377159 4.72% 73.90% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 5375832 18.42% 92.32% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 1030141 3.53% 95.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 601956 2.06% 97.92% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 392573 1.35% 99.26% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 169204 0.58% 99.84% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 46525 0.16% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 29183655 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 85386 21.51% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.51% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 184726 46.54% 68.05% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 126802 31.95% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 26465043 80.99% 80.99% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 21101 0.06% 81.06% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.06% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 20515 0.06% 81.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.12% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.13% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 3679518 11.26% 92.39% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 2182790 6.68% 99.07% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 305379 0.93% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 32678030 # Type of FU issued
system.cpu2.iq.rate 1.062371 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 396914 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 94697637 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 36112111 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 32047154 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 254329 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 120282 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 117366 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 32936079 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 136409 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 206083 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 440040 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 1257 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 6058 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 180485 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 5073 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 225988 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 193789 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 3993186 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 173385 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 35054322 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 55127 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3528507 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 2250963 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 608084 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 13021 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 119091 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 6058 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 64339 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 136180 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 200519 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 32475558 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 3570784 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 1394178 # number of nop insts executed
system.cpu2.iew.exec_refs 5736169 # number of memory reference insts executed
system.cpu2.iew.exec_branches 7344406 # Number of branches executed
system.cpu2.iew.exec_stores 2165385 # Number of stores executed
system.cpu2.iew.exec_rate 1.055788 # Inst execution rate
system.cpu2.iew.wb_sent 32207740 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 32164520 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 18733989 # num instructions producing a value
system.cpu2.iew.wb_consumers 22461298 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.045676 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.834056 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 2690484 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 194293 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 182480 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 28713100 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.125605 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.869287 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 18196306 63.37% 63.37% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 2254505 7.85% 71.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1188955 4.14% 75.37% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 5110402 17.80% 93.16% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 563606 1.96% 95.13% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 199238 0.69% 95.82% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 165515 0.58% 96.40% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 164290 0.57% 96.97% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 870283 3.03% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 28713100 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 32319619 # Number of instructions committed
system.cpu2.commit.committedOps 32319619 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 5158945 # Number of memory references committed
system.cpu2.commit.loads 3088467 # Number of loads committed
system.cpu2.commit.membars 68233 # Number of memory barriers committed
system.cpu2.commit.branches 7171529 # Number of branches committed
system.cpu2.commit.fp_insts 115750 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 30796114 # Number of committed integer instructions.
system.cpu2.commit.function_calls 241665 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 1228262 3.80% 3.80% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 25515212 78.95% 82.75% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 20642 0.06% 82.81% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.81% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 20078 0.06% 82.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.87% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.88% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 3156700 9.77% 92.64% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 2072118 6.41% 99.06% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 305379 0.94% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 32319619 # Class of committed instruction
system.cpu2.commit.bw_lim_events 870283 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 62775514 # The number of ROB reads
system.cpu2.rob.rob_writes 70489103 # The number of ROB writes
system.cpu2.timesIdled 177769 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1575881 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1745050657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 31093813 # Number of Instructions Simulated
system.cpu2.committedOps 31093813 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 0.989249 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.989249 # CPI: Total CPI of All Threads
system.cpu2.ipc 1.010867 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 1.010867 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 42649325 # number of integer regfile reads
system.cpu2.int_regfile_writes 22654905 # number of integer regfile writes
system.cpu2.fp_regfile_reads 71051 # number of floating regfile reads
system.cpu2.fp_regfile_writes 71293 # number of floating regfile writes
system.cpu2.misc_regfile_reads 5005090 # number of misc regfile reads
system.cpu2.misc_regfile_writes 273836 # number of misc regfile writes
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7317 # Transaction distribution
system.iobus.trans_dist::ReadResp 7317 # Transaction distribution
system.iobus.trans_dist::WriteReq 51362 # Transaction distribution
system.iobus.trans_dist::WriteResp 51362 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5370000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 89820170 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 8849000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
system.iocache.tags.tagsinuse 1.254241 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1693892852000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.254241 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.078390 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.078390 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040792208 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 2040792208 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles
system.iocache.overall_miss_latency::total 9418962 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49114.175202 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 49114.175202 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 54444.867052 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176792208 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 1176792208 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 5918962 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68101.400926 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68101.400926 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 337481 # number of replacements
system.l2c.tags.tagsinuse 65419.198683 # Cycle average of tags in use
system.l2c.tags.total_refs 4010491 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 402643 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 9.960414 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 54563.896309 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2274.571035 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2764.017947 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 537.574504 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 599.716909 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2426.240023 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 2253.181956 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.832579 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.034707 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.042176 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.008203 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.009151 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.037021 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.034381 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.998218 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 1020 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 5977 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 2679 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55308 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 38452030 # Number of tag accesses
system.l2c.tags.data_accesses 38452030 # Number of data accesses
system.l2c.Writeback_hits::writebacks 835740 # number of Writeback hits
system.l2c.Writeback_hits::total 835740 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 13 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 8 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 89227 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 26157 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 71638 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 187022 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 499466 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 126720 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 325465 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 951651 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 475379 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 83798 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 258654 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 817831 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 499466 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 564606 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 126720 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 109955 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 325465 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 330292 # number of demand (read+write) hits
system.l2c.demand_hits::total 1956504 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 499466 # number of overall hits
system.l2c.overall_hits::cpu0.data 564606 # number of overall hits
system.l2c.overall_hits::cpu1.inst 126720 # number of overall hits
system.l2c.overall_hits::cpu1.data 109955 # number of overall hits
system.l2c.overall_hits::cpu2.inst 325465 # number of overall hits
system.l2c.overall_hits::cpu2.data 330292 # number of overall hits
system.l2c.overall_hits::total 1956504 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 30 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 73126 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 17974 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 24645 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 115745 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 7275 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 2299 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 4804 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 14378 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 240531 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 15769 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 16968 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 273268 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst 7275 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 313657 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2299 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 33743 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 4804 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 41613 # number of demand (read+write) misses
system.l2c.demand_misses::total 403391 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 7275 # number of overall misses
system.l2c.overall_misses::cpu0.data 313657 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2299 # number of overall misses
system.l2c.overall_misses::cpu1.data 33743 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4804 # number of overall misses
system.l2c.overall_misses::cpu2.data 41613 # number of overall misses
system.l2c.overall_misses::total 403391 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu2.data 332500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 332500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu2.data 61500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 61500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1367951000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 2193367000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 3561318000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 186458500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 394826500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 581285000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 1169012500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data 1264906000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 2433918500 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 186458500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 2536963500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 394826500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3458273000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 6576521500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 186458500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 2536963500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 394826500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3458273000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 6576521500 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 835740 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 835740 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 31 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 43 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data 10 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 162353 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 44131 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 96283 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 302767 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 506741 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 129019 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 330269 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 966029 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 715910 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 99567 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 275622 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 1091099 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 506741 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 878263 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 129019 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 143698 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 330269 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 371905 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2359895 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 506741 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 878263 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 129019 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 143698 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 330269 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 371905 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2359895 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.709677 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.697674 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.450414 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.407287 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.255964 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.382291 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014356 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.017819 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.014546 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.014884 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.335979 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.158376 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.061563 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.250452 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.014356 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.357133 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.017819 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.234819 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014546 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.111891 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.170936 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.014356 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.357133 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.017819 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.234819 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014546 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.111891 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.170936 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15113.636364 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 11083.333333 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 30750 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 30750 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76107.210415 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 88998.458105 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 30768.655233 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81104.175729 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 82187.031640 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 40428.780081 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 74133.584882 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 74546.558227 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 8906.708799 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 81104.175729 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 75184.882791 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 82187.031640 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 83105.592002 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 16303.094268 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 81104.175729 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 75184.882791 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 82187.031640 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 83105.592002 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 16303.094268 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 75436 # number of writebacks
system.l2c.writebacks::total 75436 # number of writebacks
system.l2c.CleanEvict_mshr_misses::writebacks 185 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 185 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 22 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 22 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
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system.l2c.ReadExReq_mshr_misses::cpu2.data 24645 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 42619 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2299 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 4804 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 7103 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 15769 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 16968 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 32737 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2299 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 33743 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 4804 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 41613 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 82459 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2299 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 33743 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 4804 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 41613 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 82459 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1108 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1559 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 2667 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1387 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 3515 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2495 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3687 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 6182 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 607000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 607000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 41500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 41500 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1946917000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 3135128000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 163468500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 346786500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 510255000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1011322500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1095840500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 2107163000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 163468500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 2199533500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 346786500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 3042757500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 5752546000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 163468500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 2199533500 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu2.data 3042757500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 5752546000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 212604500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 314976000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 527580500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 282475000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 426484500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 708959500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 495079500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 741460500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 1236540000 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.709677 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.511628 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407287 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255964 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.140765 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007353 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.158376 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061563 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030004 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.034942 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.034942 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27590.909091 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27590.909091 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 20750 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66107.210415 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 78998.458105 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 73561.744762 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71836.547937 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64133.584882 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64582.773456 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64366.404985 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191881.317690 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202037.203335 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197817.960255 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203658.976208 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200415.648496 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.448080 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198428.657315 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201101.301871 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 200022.646393 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 7144 # Transaction distribution
system.membus.trans_dist::ReadResp 294958 # Transaction distribution
system.membus.trans_dist::WriteReq 9810 # Transaction distribution
system.membus.trans_dist::WriteResp 9810 # Transaction distribution
system.membus.trans_dist::Writeback 116948 # Transaction distribution
system.membus.trans_dist::CleanEvict 262295 # Transaction distribution
system.membus.trans_dist::UpgradeReq 165 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 167 # Transaction distribution
system.membus.trans_dist::ReadExReq 115610 # Transaction distribution
system.membus.trans_dist::ReadExResp 115610 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 287819 # Transaction distribution
system.membus.trans_dist::BadAddressError 5 # Transaction distribution
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144349 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1178267 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1303290 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30629632 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 30675200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33339520 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 157 # Total snoops (count)
system.membus.snoop_fanout::samples 841413 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 841413 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 841413 # Request fanout histogram
system.membus.reqLayer0.occupancy 11052000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 394258327 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 7000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 441332932 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2064402 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 883212 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1574760 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 43 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 53 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 302767 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 302767 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 966109 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1091169 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2897413 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214892 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7112305 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61827200 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142743552 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 204570752 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 141567 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4877075 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.028983 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.167759 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 4735723 97.10% 97.10% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 141352 2.90% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 4877075 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 1372572500 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 689392754 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 777864461 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches
system.cpu2.kern.mode_switch::user 0 # number of protection mode switches
system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu2.kern.mode_good::kernel 0
system.cpu2.kern.mode_good::user 0
system.cpu2.kern.mode_good::idle 0
system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches
system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu2.kern.swap_context 0 # number of times the context was actually changed
---------- End Simulation Statistics ----------
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