Andreas Hansson 7c18691db1 mem: Rename SimpleDRAM to a more suitable DRAMCtrl ... This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant). As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future. --HG-- rename : src/mem/SimpleDRAM.py => src/mem/DRAMCtrl.py rename : src/mem/simple_dram.cc => src/mem/dram_ctrl.cc rename : src/mem/simple_dram.hh => src/mem/dram_ctrl.hh		2014-03-23 11:12:12 -04:00
..
boot	rcs scripts: remove bbench.rcS	2013-04-02 12:46:49 -04:00
common	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	2014-03-23 11:12:12 -04:00
dram	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	2014-03-23 11:12:12 -04:00
example	config: ruby: rename _cpu_ruby_ports to _cpu_ports	2014-03-20 09:14:14 -05:00
ruby	ruby: garnet: convert network interfaces into clocked objects	2014-03-20 09:14:14 -05:00
splash2	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
topologies	config: topologies: slight code refactor	2014-02-23 19:16:15 -06:00