54cc0053f0
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
131 lines
3.5 KiB
C++
131 lines
3.5 KiB
C++
/*
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* Copyright (c) 2002-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Raasch
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*/
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#include <sstream>
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#include "base/misc.hh"
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#include "cpu/func_unit.hh"
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using namespace std;
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////////////////////////////////////////////////////////////////////////////
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//
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// The funciton unit
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//
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FuncUnit::FuncUnit()
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{
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capabilityList.reset();
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}
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// Copy constructor
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FuncUnit::FuncUnit(const FuncUnit &fu)
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{
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for (int i = 0; i < Num_OpClasses; ++i) {
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opLatencies[i] = fu.opLatencies[i];
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issueLatencies[i] = fu.issueLatencies[i];
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}
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capabilityList = fu.capabilityList;
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}
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void
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FuncUnit::addCapability(OpClass cap, unsigned oplat, unsigned issuelat)
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{
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if (issuelat == 0 || oplat == 0)
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panic("FuncUnit: you don't really want a zero-cycle latency do you?");
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capabilityList.set(cap);
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opLatencies[cap] = oplat;
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issueLatencies[cap] = issuelat;
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}
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bool
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FuncUnit::provides(OpClass capability)
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{
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return capabilityList[capability];
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}
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bitset<Num_OpClasses>
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FuncUnit::capabilities()
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{
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return capabilityList;
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}
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unsigned &
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FuncUnit::opLatency(OpClass cap)
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{
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return opLatencies[cap];
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}
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unsigned
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FuncUnit::issueLatency(OpClass capability)
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{
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return issueLatencies[capability];
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}
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////////////////////////////////////////////////////////////////////////////
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//
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// The SimObjects we use to get the FU information into the simulator
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//
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////////////////////////////////////////////////////////////////////////////
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//
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// We use 2 objects to specify this data in the INI file:
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// (1) OpDesc - Describes the operation class & latencies
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// (multiple OpDesc objects can refer to the same
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// operation classes)
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// (2) FUDesc - Describes the operations available in the unit &
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// the number of these units
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//
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//
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//
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// The operation-class description object
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//
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OpDesc *
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OpDescParams::create()
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{
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return new OpDesc(this);
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}
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//
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// The FuDesc object
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//
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FUDesc *
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FUDescParams::create()
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{
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return new FUDesc(this);
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}
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