7b8fcecf11
Changed cache size to be in bytes instead of kb so that testers can use very small caches and increase the chance of writeback races.
469 lines
15 KiB
C++
469 lines
15 KiB
C++
/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/ruby/system/CacheMemory.hh"
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// Output operator declaration
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//ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj);
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// ******************* Definitions *******************
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// Output operator definition
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ostream& operator<<(ostream& out, const CacheMemory& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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// ****************************************************************
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CacheMemory::CacheMemory(const string & name)
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: m_cache_name(name)
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{
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m_profiler_ptr = new CacheProfiler(name);
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}
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void CacheMemory::init(const vector<string> & argv)
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{
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int cache_size = -1;
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string policy;
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m_controller = NULL;
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for (uint32 i=0; i<argv.size(); i+=2) {
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if (argv[i] == "size") {
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cache_size = atoi(argv[i+1].c_str());
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} else if (argv[i] == "latency") {
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m_latency = atoi(argv[i+1].c_str());
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} else if (argv[i] == "assoc") {
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m_cache_assoc = atoi(argv[i+1].c_str());
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} else if (argv[i] == "replacement_policy") {
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policy = argv[i+1];
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} else if (argv[i] == "controller") {
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m_controller = RubySystem::getController(argv[i+1]);
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} else {
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cerr << "WARNING: CacheMemory: Unknown configuration parameter: " << argv[i] << endl;
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}
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}
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assert(cache_size != -1);
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m_cache_num_sets = (cache_size / m_cache_assoc) / RubySystem::getBlockSizeBytes();
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assert(m_cache_num_sets > 1);
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m_cache_num_set_bits = log_int(m_cache_num_sets);
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assert(m_cache_num_set_bits > 0);
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if(policy == "PSEUDO_LRU")
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m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc);
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else if (policy == "LRU")
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m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc);
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else
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assert(false);
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m_cache.setSize(m_cache_num_sets);
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m_locked.setSize(m_cache_num_sets);
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for (int i = 0; i < m_cache_num_sets; i++) {
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m_cache[i].setSize(m_cache_assoc);
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m_locked[i].setSize(m_cache_assoc);
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for (int j = 0; j < m_cache_assoc; j++) {
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m_cache[i][j] = NULL;
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m_locked[i][j] = -1;
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}
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}
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}
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CacheMemory::~CacheMemory()
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{
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if(m_replacementPolicy_ptr != NULL)
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delete m_replacementPolicy_ptr;
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delete m_profiler_ptr;
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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delete m_cache[i][j];
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}
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}
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}
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void CacheMemory::printConfig(ostream& out)
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{
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out << "Cache config: " << m_cache_name << endl;
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if (m_controller != NULL)
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out << " controller: " << m_controller->getName() << endl;
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out << " cache_associativity: " << m_cache_assoc << endl;
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out << " num_cache_sets_bits: " << m_cache_num_set_bits << endl;
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const int cache_num_sets = 1 << m_cache_num_set_bits;
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out << " num_cache_sets: " << cache_num_sets << endl;
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out << " cache_set_size_bytes: " << cache_num_sets * RubySystem::getBlockSizeBytes() << endl;
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out << " cache_set_size_Kbytes: "
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<< double(cache_num_sets * RubySystem::getBlockSizeBytes()) / (1<<10) << endl;
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out << " cache_set_size_Mbytes: "
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<< double(cache_num_sets * RubySystem::getBlockSizeBytes()) / (1<<20) << endl;
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out << " cache_size_bytes: "
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<< cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc << endl;
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out << " cache_size_Kbytes: "
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<< double(cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc) / (1<<10) << endl;
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out << " cache_size_Mbytes: "
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<< double(cache_num_sets * RubySystem::getBlockSizeBytes() * m_cache_assoc) / (1<<20) << endl;
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}
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// PRIVATE METHODS
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// convert a Address to its location in the cache
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Index CacheMemory::addressToCacheSet(const Address& address) const
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{
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assert(address == line_address(address));
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return address.bitSelect(RubySystem::getBlockSizeBits(), RubySystem::getBlockSizeBits() + m_cache_num_set_bits-1);
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int CacheMemory::findTagInSet(Index cacheSet, const Address& tag) const
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{
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assert(tag == line_address(tag));
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// search the set for the tags
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for (int i=0; i < m_cache_assoc; i++) {
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if ((m_cache[cacheSet][i] != NULL) &&
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(m_cache[cacheSet][i]->m_Address == tag) &&
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(m_cache[cacheSet][i]->m_Permission != AccessPermission_NotPresent)) {
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return i;
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}
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}
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return -1; // Not found
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int CacheMemory::findTagInSetIgnorePermissions(Index cacheSet, const Address& tag) const
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{
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assert(tag == line_address(tag));
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// search the set for the tags
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for (int i=0; i < m_cache_assoc; i++) {
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if (m_cache[cacheSet][i] != NULL && m_cache[cacheSet][i]->m_Address == tag)
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return i;
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}
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return -1; // Not found
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}
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// PUBLIC METHODS
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bool CacheMemory::tryCacheAccess(const Address& address,
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CacheRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == line_address(address));
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DEBUG_EXPR(CACHE_COMP, HighPrio, address);
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc != -1){ // Do we even have a tag match?
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AbstractCacheEntry* entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
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data_ptr = &(entry->getDataBlk());
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if(entry->m_Permission == AccessPermission_Read_Write) {
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return true;
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}
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if ((entry->m_Permission == AccessPermission_Read_Only) &&
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(type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) {
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return true;
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}
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// The line must not be accessible
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}
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data_ptr = NULL;
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return false;
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}
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bool CacheMemory::testCacheAccess(const Address& address,
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CacheRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == line_address(address));
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DEBUG_EXPR(CACHE_COMP, HighPrio, address);
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc != -1){ // Do we even have a tag match?
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AbstractCacheEntry* entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->touch(cacheSet, loc, g_eventQueue_ptr->getTime());
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data_ptr = &(entry->getDataBlk());
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return (m_cache[cacheSet][loc]->m_Permission != AccessPermission_NotPresent);
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}
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data_ptr = NULL;
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return false;
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}
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// tests to see if an address is present in the cache
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bool CacheMemory::isTagPresent(const Address& address) const
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int location = findTagInSet(cacheSet, address);
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if (location == -1) {
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// We didn't find the tag
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DEBUG_EXPR(CACHE_COMP, LowPrio, address);
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DEBUG_MSG(CACHE_COMP, LowPrio, "No tag match");
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return false;
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}
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DEBUG_EXPR(CACHE_COMP, LowPrio, address);
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DEBUG_MSG(CACHE_COMP, LowPrio, "found");
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return true;
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}
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// Returns true if there is:
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// a) a tag match on this address or there is
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// b) an unused line in the same cache "way"
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bool CacheMemory::cacheAvail(const Address& address) const
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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for (int i=0; i < m_cache_assoc; i++) {
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AbstractCacheEntry* entry = m_cache[cacheSet][i];
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if (entry != NULL) {
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if (entry->m_Address == address || // Already in the cache
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entry->m_Permission == AccessPermission_NotPresent) { // We found an empty entry
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return true;
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}
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} else {
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return true;
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}
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}
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return false;
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}
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void CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
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{
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assert(address == line_address(address));
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assert(!isTagPresent(address));
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assert(cacheAvail(address));
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DEBUG_EXPR(CACHE_COMP, HighPrio, address);
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// Find the first open slot
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Index cacheSet = addressToCacheSet(address);
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for (int i=0; i < m_cache_assoc; i++) {
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if (m_cache[cacheSet][i] == NULL ||
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m_cache[cacheSet][i]->m_Permission == AccessPermission_NotPresent) {
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m_cache[cacheSet][i] = entry; // Init entry
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m_cache[cacheSet][i]->m_Address = address;
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m_cache[cacheSet][i]->m_Permission = AccessPermission_Invalid;
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m_locked[cacheSet][i] = -1;
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m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime());
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return;
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}
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}
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ERROR_MSG("Allocate didn't find an available entry");
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}
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void CacheMemory::deallocate(const Address& address)
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{
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assert(address == line_address(address));
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assert(isTagPresent(address));
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DEBUG_EXPR(CACHE_COMP, HighPrio, address);
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Index cacheSet = addressToCacheSet(address);
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int location = findTagInSet(cacheSet, address);
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if (location != -1){
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delete m_cache[cacheSet][location];
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m_cache[cacheSet][location] = NULL;
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m_locked[cacheSet][location] = -1;
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}
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}
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// Returns with the physical address of the conflicting cache line
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Address CacheMemory::cacheProbe(const Address& address) const
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{
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assert(address == line_address(address));
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assert(!cacheAvail(address));
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Index cacheSet = addressToCacheSet(address);
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return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->m_Address;
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}
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// looks an address up in the cache
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AbstractCacheEntry& CacheMemory::lookup(const Address& address)
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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return *m_cache[cacheSet][loc];
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}
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// looks an address up in the cache
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const AbstractCacheEntry& CacheMemory::lookup(const Address& address) const
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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return *m_cache[cacheSet][loc];
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}
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AccessPermission CacheMemory::getPermission(const Address& address) const
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{
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assert(address == line_address(address));
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return lookup(address).m_Permission;
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}
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void CacheMemory::changePermission(const Address& address, AccessPermission new_perm)
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{
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assert(address == line_address(address));
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lookup(address).m_Permission = new_perm;
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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m_locked[cacheSet][loc] = -1;
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assert(getPermission(address) == new_perm);
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}
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// Sets the most recently used bit for a cache block
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void CacheMemory::setMRU(const Address& address)
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{
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Index cacheSet;
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cacheSet = addressToCacheSet(address);
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m_replacementPolicy_ptr->touch(cacheSet,
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findTagInSet(cacheSet, address),
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g_eventQueue_ptr->getTime());
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}
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void CacheMemory::profileMiss(const CacheMsg & msg)
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{
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m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(),
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msg.getSize(), msg.getPrefetch());
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}
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void CacheMemory::recordCacheContents(CacheRecorder& tr) const
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{
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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AccessPermission perm = m_cache[i][j]->m_Permission;
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CacheRequestType request_type = CacheRequestType_NULL;
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if (perm == AccessPermission_Read_Only) {
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if (m_is_instruction_only_cache) {
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request_type = CacheRequestType_IFETCH;
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} else {
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request_type = CacheRequestType_LD;
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}
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} else if (perm == AccessPermission_Read_Write) {
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request_type = CacheRequestType_ST;
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}
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if (request_type != CacheRequestType_NULL) {
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// tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
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// Address(0), request_type, m_replacementPolicy_ptr->getLastAccess(i, j));
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}
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}
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}
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}
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void CacheMemory::print(ostream& out) const
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{
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out << "Cache dump: " << m_cache_name << endl;
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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if (m_cache[i][j] != NULL) {
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out << " Index: " << i
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<< " way: " << j
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<< " entry: " << *m_cache[i][j] << endl;
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} else {
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out << " Index: " << i
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<< " way: " << j
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<< " entry: NULL" << endl;
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}
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}
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}
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}
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void CacheMemory::printData(ostream& out) const
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{
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out << "printData() not supported" << endl;
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}
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void CacheMemory::clearStats() const
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{
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m_profiler_ptr->clearStats();
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}
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void CacheMemory::printStats(ostream& out) const
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{
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m_profiler_ptr->printStats(out);
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}
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void CacheMemory::getMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes ){
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AbstractCacheEntry& entry = lookup(line_address(addr));
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unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
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for(unsigned int i=0; i<size_in_bytes; ++i){
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value[i] = entry.getDataBlk().getByte(i + startByte);
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}
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}
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void CacheMemory::setMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes ){
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AbstractCacheEntry& entry = lookup(line_address(addr));
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unsigned int startByte = addr.getAddress() - line_address(addr).getAddress();
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assert(size_in_bytes > 0);
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for(unsigned int i=0; i<size_in_bytes; ++i){
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entry.getDataBlk().setByte(i + startByte, value[i]);
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}
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// entry = lookup(line_address(addr));
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}
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void
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CacheMemory::setLocked(const Address& address, int context)
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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m_locked[cacheSet][loc] = context;
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}
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void
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CacheMemory::clearLocked(const Address& address)
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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m_locked[cacheSet][loc] = -1;
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}
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bool
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CacheMemory::isLocked(const Address& address, int context)
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{
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assert(address == line_address(address));
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Index cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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return m_locked[cacheSet][loc] == context;
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}
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