7b6cf951e2
Turns out that SPARC SE mode relied on M5_pid being "0" in all cases. The entries in the SPARC TLBs are accessed with M5_pid as their context. This is buggy in the sense that it will never work with more than one process or any initialization that doesn't have the M5_pid value passed in as "0". cd7f3a1dbf55 broke the SPARC build because it deletes M5_pid and uses a _pid with a default of "100" instead. This caused the SPARC TLB to never return any valid lookups for any request; the program never moved past the first instruction with SPARC SE in the regression tester. The solution proposed in this changeset is to initialize the address space identification register with the PID value that is passed into the process class as a parameter from Python. This should return the correct responses from the TLB since the insertions and lookups into the page table will be using the same PID. Furthermore, there are corner cases in the code which elevate privileges and revert to using context "0" as the context in the TLB. I believe that these are related to kernel level traps and hypervisor privilege escalations, but I'm not completely sure. I've tried to address the corner cases properly, but it would be beneficial to have someone who is familiar with the SPARC architecture to take a look at this fix.
827 lines
28 KiB
C++
827 lines
28 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Kevin Lim
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*/
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#include "arch/sparc/faults.hh"
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#include <algorithm>
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/process.hh"
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#include "arch/sparc/types.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "mem/page_table.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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using namespace std;
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namespace SparcISA
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{
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template<> SparcFaultBase::FaultVals
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SparcFault<PowerOnReset>::vals =
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{"power_on_reset", 0x001, 0, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<WatchDogReset>::vals =
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{"watch_dog_reset", 0x002, 120, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<ExternallyInitiatedReset>::vals =
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{"externally_initiated_reset", 0x003, 110, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<SoftwareInitiatedReset>::vals =
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{"software_initiated_reset", 0x004, 130, {SH, SH, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<REDStateException>::vals =
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{"RED_state_exception", 0x005, 1, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<StoreError>::vals =
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{"store_error", 0x007, 201, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionAccessException>::vals =
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{"instruction_access_exception", 0x008, 300, {H, H, H}, FaultStat()};
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<InstructionAccessMMUMiss>::vals =
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{"inst_mmu", 0x009, 2, {H, H, H}};*/
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionAccessError>::vals =
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{"instruction_access_error", 0x00A, 400, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<IllegalInstruction>::vals =
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{"illegal_instruction", 0x010, 620, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<PrivilegedOpcode>::vals =
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{"privileged_opcode", 0x011, 700, {P, SH, SH}, FaultStat()};
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<UnimplementedLDD>::vals =
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{"unimp_ldd", 0x012, 6, {H, H, H}};*/
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<UnimplementedSTD>::vals =
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{"unimp_std", 0x013, 6, {H, H, H}};*/
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template<> SparcFaultBase::FaultVals
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SparcFault<FpDisabled>::vals =
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{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<FpExceptionIEEE754>::vals =
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{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<FpExceptionOther>::vals =
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{"fp_exception_other", 0x022, 1110, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<TagOverflow>::vals =
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{"tag_overflow", 0x023, 1400, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<CleanWindow>::vals =
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{"clean_window", 0x024, 1010, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<DivisionByZero>::vals =
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{"division_by_zero", 0x028, 1500, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<InternalProcessorError>::vals =
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{"internal_processor_error", 0x029, 4, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionInvalidTSBEntry>::vals =
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{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<DataInvalidTSBEntry>::vals =
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{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessException>::vals =
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{"data_access_exception", 0x030, 1201, {H, H, H}, FaultStat()};
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessMMUMiss>::vals =
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{"data_mmu", 0x031, 12, {H, H, H}};*/
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template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessError>::vals =
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{"data_access_error", 0x032, 1210, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<DataAccessProtection>::vals =
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{"data_access_protection", 0x033, 1207, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<MemAddressNotAligned>::vals =
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{"mem_address_not_aligned", 0x034, 1020, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<LDDFMemAddressNotAligned>::vals =
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{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<STDFMemAddressNotAligned>::vals =
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{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<PrivilegedAction>::vals =
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{"privileged_action", 0x037, 1110, {H, H, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<LDQFMemAddressNotAligned>::vals =
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{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<STQFMemAddressNotAligned>::vals =
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{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionRealTranslationMiss>::vals =
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{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<DataRealTranslationMiss>::vals =
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{"data_real_translation_miss", 0x03F, 1203, {H, H, H}, FaultStat()};
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//XXX This trap is apparently dropped from ua2005
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/*template<> SparcFaultBase::FaultVals
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SparcFault<AsyncDataError>::vals =
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{"async_data", 0x040, 2, {H, H, H}};*/
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template<> SparcFaultBase::FaultVals
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SparcFault<InterruptLevelN>::vals =
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{"interrupt_level_n", 0x040, 0, {P, P, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<HstickMatch>::vals =
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{"hstick_match", 0x05E, 1601, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<TrapLevelZero>::vals =
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{"trap_level_zero", 0x05F, 202, {H, H, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<InterruptVector>::vals =
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{"interrupt_vector", 0x060, 2630, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<PAWatchpoint>::vals =
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{"PA_watchpoint", 0x061, 1209, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<VAWatchpoint>::vals =
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{"VA_watchpoint", 0x062, 1120, {P, P, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<FastInstructionAccessMMUMiss>::vals =
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{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<FastDataAccessMMUMiss>::vals =
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{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<FastDataAccessProtection>::vals =
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{"fast_data_access_protection", 0x06C, 1207, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<InstructionBreakpoint>::vals =
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{"instruction_break", 0x076, 610, {H, H, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<CpuMondo>::vals =
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{"cpu_mondo", 0x07C, 1608, {P, P, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<DevMondo>::vals =
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{"dev_mondo", 0x07D, 1611, {P, P, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<ResumableError>::vals =
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{"resume_error", 0x07E, 3330, {P, P, SH}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<SpillNNormal>::vals =
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{"spill_n_normal", 0x080, 900, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<SpillNOther>::vals =
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{"spill_n_other", 0x0A0, 900, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<FillNNormal>::vals =
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{"fill_n_normal", 0x0C0, 900, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<FillNOther>::vals =
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{"fill_n_other", 0x0E0, 900, {P, P, H}, FaultStat()};
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template<> SparcFaultBase::FaultVals
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SparcFault<TrapInstruction>::vals =
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{"trap_instruction", 0x100, 1602, {P, P, H}, FaultStat()};
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/**
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* This causes the thread context to enter RED state. This causes the side
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* effects which go with entering RED state because of a trap.
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*/
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void
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enterREDState(ThreadContext *tc)
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{
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//@todo Disable the mmu?
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//@todo Disable watchpoints?
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HPSTATE hpstate= tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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hpstate.red = 1;
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hpstate.hpriv = 1;
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tc->setMiscReg(MISCREG_HPSTATE, hpstate);
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// PSTATE.priv is set to 1 here. The manual says it should be 0, but
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// Legion sets it to 1.
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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pstate.priv = 1;
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tc->setMiscReg(MISCREG_PSTATE, pstate);
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}
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/**
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* This sets everything up for a RED state trap except for actually jumping to
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* the handler.
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*/
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void
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doREDFault(ThreadContext *tc, TrapType tt)
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{
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MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
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MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
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MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
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MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
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MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
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MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
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PCState pc = tc->pcState();
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TL++;
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Addr pcMask = pstate.am ? mask(32) : mask(64);
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// set TSTATE.gl to gl
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replaceBits(TSTATE, 42, 40, GL);
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// set TSTATE.ccr to ccr
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replaceBits(TSTATE, 39, 32, CCR);
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// set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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// set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, pstate);
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// set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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// Write back TSTATE
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tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
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// set TPC to PC
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tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
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// set TNPC to NPC
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tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
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// set HTSTATE.hpstate to hpstate
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tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
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// TT = trap type;
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tc->setMiscRegNoEffect(MISCREG_TT, tt);
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// Update GL
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tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
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bool priv = pstate.priv; // just save the priv bit
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pstate = 0;
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pstate.priv = priv;
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pstate.pef = 1;
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tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
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hpstate.red = 1;
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hpstate.hpriv = 1;
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hpstate.ibe = 0;
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hpstate.tlz = 0;
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tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
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bool changedCWP = true;
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if (tt == 0x24)
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CWP++;
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else if (0x80 <= tt && tt <= 0xbf)
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CWP += (CANSAVE + 2);
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else if (0xc0 <= tt && tt <= 0xff)
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CWP--;
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else
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changedCWP = false;
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if (changedCWP) {
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CWP = (CWP + NWindows) % NWindows;
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tc->setMiscReg(MISCREG_CWP, CWP);
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}
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}
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/**
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* This sets everything up for a normal trap except for actually jumping to
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* the handler.
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*/
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void
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doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
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{
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MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
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MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
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PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
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HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
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MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
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MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
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MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
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MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
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MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
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PCState pc = tc->pcState();
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// Increment the trap level
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TL++;
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tc->setMiscRegNoEffect(MISCREG_TL, TL);
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Addr pcMask = pstate.am ? mask(32) : mask(64);
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// Save off state
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// set TSTATE.gl to gl
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replaceBits(TSTATE, 42, 40, GL);
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// set TSTATE.ccr to ccr
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replaceBits(TSTATE, 39, 32, CCR);
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// set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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// set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, pstate);
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// set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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// Write back TSTATE
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tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
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// set TPC to PC
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tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask);
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// set TNPC to NPC
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tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask);
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|
|
// set HTSTATE.hpstate to hpstate
|
|
tc->setMiscRegNoEffect(MISCREG_HTSTATE, hpstate);
|
|
|
|
// TT = trap type;
|
|
tc->setMiscRegNoEffect(MISCREG_TT, tt);
|
|
|
|
// Update the global register level
|
|
if (!gotoHpriv)
|
|
tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
|
|
else
|
|
tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
|
|
|
|
// pstate.mm is unchanged
|
|
pstate.pef = 1; // PSTATE.pef = whether or not an fpu is present
|
|
pstate.am = 0;
|
|
pstate.ie = 0;
|
|
// pstate.tle is unchanged
|
|
// pstate.tct = 0
|
|
|
|
if (gotoHpriv) {
|
|
pstate.cle = 0;
|
|
// The manual says PSTATE.priv should be 0, but Legion leaves it alone
|
|
hpstate.red = 0;
|
|
hpstate.hpriv = 1;
|
|
hpstate.ibe = 0;
|
|
// hpstate.tlz is unchanged
|
|
tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
|
|
} else { // we are going to priv
|
|
pstate.priv = 1;
|
|
pstate.cle = pstate.tle;
|
|
}
|
|
tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
|
|
|
|
|
|
bool changedCWP = true;
|
|
if (tt == 0x24)
|
|
CWP++;
|
|
else if (0x80 <= tt && tt <= 0xbf)
|
|
CWP += (CANSAVE + 2);
|
|
else if (0xc0 <= tt && tt <= 0xff)
|
|
CWP--;
|
|
else
|
|
changedCWP = false;
|
|
|
|
if (changedCWP) {
|
|
CWP = (CWP + NWindows) % NWindows;
|
|
tc->setMiscReg(MISCREG_CWP, CWP);
|
|
}
|
|
}
|
|
|
|
void
|
|
getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
|
|
{
|
|
//XXX The following constant might belong in a header file.
|
|
const Addr RSTVAddr = 0xFFF0000000ULL;
|
|
PC = RSTVAddr | ((TT << 5) & 0xFF);
|
|
NPC = PC + sizeof(MachInst);
|
|
}
|
|
|
|
void
|
|
getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
|
|
{
|
|
Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
|
|
PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
|
|
NPC = PC + sizeof(MachInst);
|
|
}
|
|
|
|
void
|
|
getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
|
|
{
|
|
Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
|
|
PC = (TBA & ~mask(15)) |
|
|
(TL > 1 ? (1 << 14) : 0) |
|
|
((TT << 5) & mask(14));
|
|
NPC = PC + sizeof(MachInst);
|
|
}
|
|
|
|
void
|
|
SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
|
|
{
|
|
FaultBase::invoke(tc);
|
|
if (!FullSystem)
|
|
return;
|
|
|
|
countStat()++;
|
|
|
|
// We can refer to this to see what the trap level -was-, but something
|
|
// in the middle could change it in the regfile out from under us.
|
|
MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
|
|
MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
|
|
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
|
|
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
|
|
|
|
Addr PC, NPC;
|
|
|
|
PrivilegeLevel current;
|
|
if (hpstate.hpriv)
|
|
current = Hyperprivileged;
|
|
else if (pstate.priv)
|
|
current = Privileged;
|
|
else
|
|
current = User;
|
|
|
|
PrivilegeLevel level = getNextLevel(current);
|
|
|
|
if (hpstate.red || (tl == MaxTL - 1)) {
|
|
getREDVector(5, PC, NPC);
|
|
doREDFault(tc, tt);
|
|
// This changes the hpstate and pstate, so we need to make sure we
|
|
// save the old version on the trap stack in doREDFault.
|
|
enterREDState(tc);
|
|
} else if (tl == MaxTL) {
|
|
panic("Should go to error state here.. crap\n");
|
|
// Do error_state somehow?
|
|
// Probably inject a WDR fault using the interrupt mechanism.
|
|
// What should the PC and NPC be set to?
|
|
} else if (tl > MaxPTL && level == Privileged) {
|
|
// guest_watchdog fault
|
|
doNormalFault(tc, trapType(), true);
|
|
getHyperVector(tc, PC, NPC, 2);
|
|
} else if (level == Hyperprivileged ||
|
|
(level == Privileged && trapType() >= 384)) {
|
|
doNormalFault(tc, trapType(), true);
|
|
getHyperVector(tc, PC, NPC, trapType());
|
|
} else {
|
|
doNormalFault(tc, trapType(), false);
|
|
getPrivVector(tc, PC, NPC, trapType(), tl + 1);
|
|
}
|
|
|
|
PCState pc;
|
|
pc.pc(PC);
|
|
pc.npc(NPC);
|
|
pc.nnpc(NPC + sizeof(MachInst));
|
|
pc.upc(0);
|
|
pc.nupc(1);
|
|
tc->pcState(pc);
|
|
}
|
|
|
|
void
|
|
PowerOnReset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
|
|
{
|
|
// For SPARC, when a system is first started, there is a power
|
|
// on reset Trap which sets the processor into the following state.
|
|
// Bits that aren't set aren't defined on startup.
|
|
|
|
tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
|
|
tc->setMiscRegNoEffect(MISCREG_TT, trapType());
|
|
tc->setMiscReg(MISCREG_GL, MaxGL);
|
|
|
|
PSTATE pstate = 0;
|
|
pstate.pef = 1;
|
|
pstate.priv = 1;
|
|
tc->setMiscRegNoEffect(MISCREG_PSTATE, pstate);
|
|
|
|
// Turn on red and hpriv, set everything else to 0
|
|
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
|
|
hpstate.red = 1;
|
|
hpstate.hpriv = 1;
|
|
hpstate.ibe = 0;
|
|
hpstate.tlz = 0;
|
|
tc->setMiscRegNoEffect(MISCREG_HPSTATE, hpstate);
|
|
|
|
// The tick register is unreadable by nonprivileged software
|
|
tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
|
|
|
|
// Enter RED state. We do this last so that the actual state preserved in
|
|
// the trap stack is the state from before this fault.
|
|
enterREDState(tc);
|
|
|
|
Addr PC, NPC;
|
|
getREDVector(trapType(), PC, NPC);
|
|
|
|
PCState pc;
|
|
pc.pc(PC);
|
|
pc.npc(NPC);
|
|
pc.nnpc(NPC + sizeof(MachInst));
|
|
pc.upc(0);
|
|
pc.nupc(1);
|
|
tc->pcState(pc);
|
|
|
|
// These registers are specified as "undefined" after a POR, and they
|
|
// should have reasonable values after the miscregfile is reset
|
|
/*
|
|
// Clear all the soft interrupt bits
|
|
softint = 0;
|
|
// disable timer compare interrupts, reset tick_cmpr
|
|
tc->setMiscRegNoEffect(MISCREG_
|
|
tick_cmprFields.int_dis = 1;
|
|
tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
|
|
stickFields.npt = 1; // The TICK register is unreadable by by !priv
|
|
stick_cmprFields.int_dis = 1; // disable timer compare interrupts
|
|
stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
|
|
|
|
tt[tl] = _trapType;
|
|
|
|
hintp = 0; // no interrupts pending
|
|
hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
|
|
hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
|
|
*/
|
|
}
|
|
|
|
void
|
|
FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
|
|
const StaticInstPtr &inst)
|
|
{
|
|
if (FullSystem) {
|
|
SparcFaultBase::invoke(tc, inst);
|
|
return;
|
|
}
|
|
|
|
Process *p = tc->getProcessPtr();
|
|
TlbEntry entry;
|
|
bool success = p->pTable->lookup(vaddr, entry);
|
|
if (!success) {
|
|
panic("Tried to execute unmapped address %#x.\n", vaddr);
|
|
} else {
|
|
Addr alignedvaddr = p->pTable->pageAlign(vaddr);
|
|
|
|
// Grab fields used during instruction translation to figure out
|
|
// which context to use.
|
|
uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
|
|
|
|
// Inside a VM, a real address is the address that guest OS would
|
|
// interpret to be a physical address. To map to the physical address,
|
|
// it still needs to undergo a translation. The instruction
|
|
// translation code in the SPARC ITLB code assumes that the context is
|
|
// zero (kernel-level) if real addressing is being used.
|
|
bool is_real_address = !bits(tlbdata, 4);
|
|
|
|
// The SPARC ITLB code assumes that traps are executed in context
|
|
// zero so we carry that assumption through here.
|
|
bool trapped = bits(tlbdata, 18, 16) > 0;
|
|
|
|
// The primary context acts as a PASID. It allows the MMU to
|
|
// distinguish between virtual addresses that would alias to the
|
|
// same physical address (if two or more processes shared the same
|
|
// virtual address mapping).
|
|
int primary_context = bits(tlbdata, 47, 32);
|
|
|
|
// The partition id distinguishes between virtualized environments.
|
|
int const partition_id = 0;
|
|
|
|
// Given the assumptions in the translateInst code in the SPARC ITLB,
|
|
// the logic works out to the following for the context.
|
|
int context_id = (is_real_address || trapped) ? 0 : primary_context;
|
|
|
|
// Insert the TLB entry.
|
|
// The entry specifying whether the address is "real" is set to
|
|
// false for syscall emulation mode regardless of whether the
|
|
// address is real in preceding code. Not sure sure that this is
|
|
// correct, but also not sure if it matters at all.
|
|
tc->getITBPtr()->insert(alignedvaddr, partition_id, context_id,
|
|
false, entry.pte);
|
|
}
|
|
}
|
|
|
|
void
|
|
FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
|
|
{
|
|
if (FullSystem) {
|
|
SparcFaultBase::invoke(tc, inst);
|
|
return;
|
|
}
|
|
|
|
Process *p = tc->getProcessPtr();
|
|
TlbEntry entry;
|
|
bool success = p->pTable->lookup(vaddr, entry);
|
|
if (!success) {
|
|
if (p->fixupStackFault(vaddr))
|
|
success = p->pTable->lookup(vaddr, entry);
|
|
}
|
|
if (!success) {
|
|
panic("Tried to access unmapped address %#x.\n", vaddr);
|
|
} else {
|
|
Addr alignedvaddr = p->pTable->pageAlign(vaddr);
|
|
|
|
// Grab fields used during data translation to figure out
|
|
// which context to use.
|
|
uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
|
|
|
|
// The primary context acts as a PASID. It allows the MMU to
|
|
// distinguish between virtual addresses that would alias to the
|
|
// same physical address (if two or more processes shared the same
|
|
// virtual address mapping). There's a secondary context used in the
|
|
// DTLB translation code, but it should __probably__ be zero for
|
|
// syscall emulation code. (The secondary context is used by Solaris
|
|
// to allow kernel privilege code to access user space code:
|
|
// [ISBN 0-13-022496-0]:PG199.)
|
|
int primary_context = bits(tlbdata, 47, 32);
|
|
|
|
// "Hyper-Privileged Mode" is in use. There are three main modes of
|
|
// operation for Sparc: Hyper-Privileged Mode, Privileged Mode, and
|
|
// User Mode.
|
|
int hpriv = bits(tlbdata, 0);
|
|
|
|
// Reset, Error and Debug state is in use. Something horrible has
|
|
// happened or the system is operating in Reset Mode.
|
|
int red = bits(tlbdata, 1);
|
|
|
|
// Inside a VM, a real address is the address that guest OS would
|
|
// interpret to be a physical address. To map to the physical address,
|
|
// it still needs to undergo a translation. The instruction
|
|
// translation code in the SPARC ITLB code assumes that the context is
|
|
// zero (kernel-level) if real addressing is being used.
|
|
int is_real_address = !bits(tlbdata, 5);
|
|
|
|
// Grab the address space identifier register from the thread context.
|
|
// XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
|
|
// MISCREG_ASI causes me to think that the ASI register implementation
|
|
// might be bugged. The NoEffect variant changes the ASI register
|
|
// value in the architectural state while the normal variant changes
|
|
// the context field in the thread context's currently decoded request
|
|
// but does not directly affect the ASI register value in the
|
|
// architectural state. The ASI values and the context field in the
|
|
// request packet seem to have completely different uses.
|
|
MiscReg reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
|
|
ASI asi = static_cast<ASI>(reg_asi);
|
|
|
|
// The SPARC DTLB code assumes that traps are executed in context
|
|
// zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also
|
|
// an assumption that the nucleus address space is being used, but
|
|
// the context is the relevant issue since we need to pass it to TLB.
|
|
bool trapped = bits(tlbdata, 18, 16) > 0;
|
|
|
|
// Given the assumptions in the translateData code in the SPARC DTLB,
|
|
// the logic works out to the following for the context.
|
|
int context_id = ((!hpriv && !red && is_real_address) ||
|
|
asiIsReal(asi) ||
|
|
(trapped && asi == ASI_IMPLICIT))
|
|
? 0 : primary_context;
|
|
|
|
// The partition id distinguishes between virtualized environments.
|
|
int const partition_id = 0;
|
|
|
|
// Insert the TLB entry.
|
|
// The entry specifying whether the address is "real" is set to
|
|
// false for syscall emulation mode regardless of whether the
|
|
// address is real in preceding code. Not sure sure that this is
|
|
// correct, but also not sure if it matters at all.
|
|
tc->getDTBPtr()->insert(alignedvaddr, partition_id, context_id,
|
|
false, entry.pte);
|
|
}
|
|
}
|
|
|
|
void
|
|
SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
|
|
{
|
|
if (FullSystem) {
|
|
SparcFaultBase::invoke(tc, inst);
|
|
return;
|
|
}
|
|
|
|
doNormalFault(tc, trapType(), false);
|
|
|
|
Process *p = tc->getProcessPtr();
|
|
|
|
//XXX This will only work in faults from a SparcLiveProcess
|
|
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
|
|
assert(lp);
|
|
|
|
// Then adjust the PC and NPC
|
|
tc->pcState(lp->readSpillStart());
|
|
}
|
|
|
|
void
|
|
FillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
|
|
{
|
|
if (FullSystem) {
|
|
SparcFaultBase::invoke(tc, inst);
|
|
return;
|
|
}
|
|
|
|
doNormalFault(tc, trapType(), false);
|
|
|
|
Process *p = tc->getProcessPtr();
|
|
|
|
//XXX This will only work in faults from a SparcLiveProcess
|
|
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
|
|
assert(lp);
|
|
|
|
// Then adjust the PC and NPC
|
|
tc->pcState(lp->readFillStart());
|
|
}
|
|
|
|
void
|
|
TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
|
|
{
|
|
if (FullSystem) {
|
|
SparcFaultBase::invoke(tc, inst);
|
|
return;
|
|
}
|
|
|
|
// In SE, this mechanism is how the process requests a service from
|
|
// the operating system. We'll get the process object from the thread
|
|
// context and let it service the request.
|
|
|
|
Process *p = tc->getProcessPtr();
|
|
|
|
SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
|
|
assert(lp);
|
|
|
|
lp->handleTrap(_n, tc);
|
|
|
|
// We need to explicitly advance the pc, since that's not done for us
|
|
// on a faulting instruction
|
|
PCState pc = tc->pcState();
|
|
pc.advance();
|
|
tc->pcState(pc);
|
|
}
|
|
|
|
} // namespace SparcISA
|
|
|