Also various changes to make the CPU model less ISA dependent, which includes moving the code that checks for interrupts up to the ISA level, moving code that zeroes the zero registers up to the ISA level, and removing opcode and ra from the regfile. arch/alpha/alpha_memory.cc: The regfile has been changed so it no longer has the opcode and ra. Instead the xc holds the actual instruction, and from there the opcode and ra can be obtained with OPCODE() and RA(). arch/alpha/ev5.cc: Moved code that once existed within simpleCPU to ev5, and templatized it. This way the CPU models can call processInterrupts and the ISA specific interrupt handling is left to the ISA's code. Also moved ISA specific zero registers from simpleCPU to here. arch/alpha/ev5.hh: Added macros for obtaining the opcode and ra from the instruction itself, as there is no longer opcode or ra in the regfile. arch/alpha/isa_desc: Added in declarations for the FastCPU model. arch/alpha/isa_traits.hh: Removed opcode and ra from the regfile. The xc now holds the actual instruction, and the opcode and ra can be obtained through it. Also added the declaration for the templated zeroRegisters() function, which will set the zero registers to 0. arch/isa_parser.py: Added in FastCPUExecContext so it will generate code for the FastCPU model as well. cpu/exec_context.cc: Added in a more generic trap function so "ev5_trap" doesn't need to be called. It currently still calls the old method, with plans for making this ISA dependent in the future. cpu/exec_context.hh: Exec context now has the instruction within it. Also added methods for exec context to read an instruction from memory, return the current instruction, and set the instruction if needed. Also has declaration for more generic trap() function. cpu/simple_cpu/simple_cpu.cc: Removed references to opcode and ra, and instead sets the xc's instruction with the fetched instruction. cpu/static_inst.hh: Added declaration for execute() using FastCPUExecContext. --HG-- extra : convert_revision : 0441ea3700ac50b733e485395d4dd4ac83666f92
607 lines
16 KiB
C++
607 lines
16 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sstream>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "sim/builder.hh"
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#include "targetarch/alpha_memory.hh"
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#include "targetarch/ev5.hh"
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using namespace std;
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha TLB
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//
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AlphaTLB::AlphaTLB(const string &name, int s)
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: SimObject(name), size(s), nlu(0)
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{
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table = new AlphaISA::PTE[size];
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memset(table, 0, sizeof(AlphaISA::PTE[size]));
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}
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AlphaTLB::~AlphaTLB()
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{
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if (table)
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delete [] table;
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}
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// look up an entry in the TLB
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AlphaISA::PTE *
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AlphaTLB::lookup(Addr vpn, uint8_t asn) const
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{
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DPRINTF(TLB, "lookup %#x\n", vpn);
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PageTable::const_iterator i = lookupTable.find(vpn);
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if (i == lookupTable.end())
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return NULL;
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while (i->first == vpn) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (vpn == pte->tag && (pte->asma || pte->asn == asn))
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return pte;
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++i;
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}
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// not found...
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return NULL;
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}
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void
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AlphaTLB::checkCacheability(MemReqPtr &req)
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{
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// in Alpha, cacheability is controlled by upper-level bits of the
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// physical address
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if (req->paddr & PA_UNCACHED_BIT) {
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if (PA_IPR_SPACE(req->paddr)) {
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// IPR memory space not implemented
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if (!req->xc->misspeculating()) {
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switch (req->paddr) {
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case ULL(0xFFFFF00188):
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req->data = 0;
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break;
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default:
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panic("IPR memory space not implemented! PA=%x\n",
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req->paddr);
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}
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}
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} else {
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// mark request as uncacheable
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req->flags |= UNCACHEABLE;
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}
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}
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}
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// insert a new TLB entry
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void
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AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte)
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{
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if (table[nlu].valid) {
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Addr oldvpn = table[nlu].tag;
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PageTable::iterator i = lookupTable.find(oldvpn);
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if (i == lookupTable.end())
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panic("TLB entry not found in lookupTable");
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int index;
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while ((index = i->second) != nlu) {
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if (table[index].tag != oldvpn)
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panic("TLB entry not found in lookupTable");
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++i;
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}
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DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
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lookupTable.erase(i);
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}
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Addr vpn = VA_VPN(vaddr);
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DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vpn, pte.ppn);
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table[nlu] = pte;
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table[nlu].tag = vpn;
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table[nlu].valid = true;
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lookupTable.insert(make_pair(vpn, nlu));
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nextnlu();
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}
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void
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AlphaTLB::flushAll()
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{
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memset(table, 0, sizeof(AlphaISA::PTE[size]));
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lookupTable.clear();
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nlu = 0;
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}
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void
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AlphaTLB::flushProcesses()
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{
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PageTable::iterator i = lookupTable.begin();
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PageTable::iterator end = lookupTable.end();
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while (i != end) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (!pte->asma) {
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DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, pte->tag, pte->ppn);
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pte->valid = false;
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lookupTable.erase(i);
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}
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++i;
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}
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}
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void
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AlphaTLB::flushAddr(Addr vaddr, uint8_t asn)
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{
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Addr vpn = VA_VPN(vaddr);
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PageTable::iterator i = lookupTable.find(vpn);
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if (i == lookupTable.end())
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return;
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while (i->first == vpn) {
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int index = i->second;
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AlphaISA::PTE *pte = &table[index];
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assert(pte->valid);
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if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
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DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vpn, pte->ppn);
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// invalidate this entry
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pte->valid = false;
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lookupTable.erase(i);
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}
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++i;
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}
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}
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void
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AlphaTLB::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(size);
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SERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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nameOut(os, csprintf("%s.PTE%d", name(), i));
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table[i].serialize(os);
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}
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}
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void
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AlphaTLB::unserialize(Checkpoint *cp, const string §ion)
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{
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UNSERIALIZE_SCALAR(size);
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UNSERIALIZE_SCALAR(nlu);
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for (int i = 0; i < size; i++) {
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table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
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if (table[i].valid) {
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lookupTable.insert(make_pair(table[i].tag, i));
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}
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}
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha ITB
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//
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AlphaITB::AlphaITB(const std::string &name, int size)
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: AlphaTLB(name, size)
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{}
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void
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AlphaITB::regStats()
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{
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hits
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.name(name() + ".hits")
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.desc("ITB hits");
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misses
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.name(name() + ".misses")
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.desc("ITB misses");
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acv
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.name(name() + ".acv")
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.desc("ITB acv");
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accesses
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.name(name() + ".accesses")
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.desc("ITB accesses");
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accesses = hits + misses;
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}
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void
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AlphaITB::fault(Addr pc, ExecContext *xc) const
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{
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uint64_t *ipr = xc->regs.ipr;
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if (!xc->misspeculating()) {
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ipr[AlphaISA::IPR_ITB_TAG] = pc;
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ipr[AlphaISA::IPR_IFAULT_VA_FORM] =
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ipr[AlphaISA::IPR_IVPTBR] | (VA_VPN(pc) << 3);
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}
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}
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Fault
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AlphaITB::translate(MemReqPtr &req) const
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{
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InternalProcReg *ipr = req->xc->regs.ipr;
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if (PC_PAL(req->vaddr)) {
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// strip off PAL PC marker (lsb is 1)
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req->paddr = (req->vaddr & ~3) & PA_IMPL_MASK;
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hits++;
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return No_Fault;
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}
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if (req->flags & PHYSICAL) {
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req->paddr = req->vaddr;
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} else {
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// verify that this is a good virtual address
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if (!validVirtualAddress(req->vaddr)) {
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fault(req->vaddr, req->xc);
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acv++;
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return ITB_Acv_Fault;
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}
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// Check for "superpage" mapping: when SP<1> is set, and
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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VA_SPACE(req->vaddr) == 2) {
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// only valid in kernel mode
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if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
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fault(req->vaddr, req->xc);
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acv++;
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return ITB_Acv_Fault;
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}
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req->paddr = req->vaddr & PA_IMPL_MASK;
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} else {
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// not a physical address: need to look up pte
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AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
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DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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if (!pte) {
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fault(req->vaddr, req->xc);
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misses++;
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return ITB_Fault_Fault;
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}
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req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3);
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// check permissions for this access
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if (!(pte->xre & (1 << ICM_CM(ipr[AlphaISA::IPR_ICM])))) {
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// instruction access fault
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fault(req->vaddr, req->xc);
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acv++;
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return ITB_Acv_Fault;
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}
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hits++;
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}
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}
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// check that the physical address is ok (catch bad physical addresses)
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if (req->paddr & ~PA_IMPL_MASK)
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return Machine_Check_Fault;
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checkCacheability(req);
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return No_Fault;
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}
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///////////////////////////////////////////////////////////////////////
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//
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// Alpha DTB
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//
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AlphaDTB::AlphaDTB(const std::string &name, int size)
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: AlphaTLB(name, size)
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{}
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void
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AlphaDTB::regStats()
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{
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read_hits
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.name(name() + ".read_hits")
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.desc("DTB read hits")
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;
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read_misses
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.name(name() + ".read_misses")
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.desc("DTB read misses")
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;
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read_acv
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.name(name() + ".read_acv")
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.desc("DTB read access violations")
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;
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read_accesses
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.name(name() + ".read_accesses")
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.desc("DTB read accesses")
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;
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write_hits
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.name(name() + ".write_hits")
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.desc("DTB write hits")
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;
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write_misses
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.name(name() + ".write_misses")
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.desc("DTB write misses")
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;
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write_acv
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.name(name() + ".write_acv")
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.desc("DTB write access violations")
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;
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write_accesses
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.name(name() + ".write_accesses")
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.desc("DTB write accesses")
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;
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hits
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.name(name() + ".hits")
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.desc("DTB hits")
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;
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misses
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.name(name() + ".misses")
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.desc("DTB misses")
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;
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acv
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.name(name() + ".acv")
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.desc("DTB access violations")
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;
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accesses
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.name(name() + ".accesses")
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.desc("DTB accesses")
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;
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hits = read_hits + write_hits;
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misses = read_misses + write_misses;
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acv = read_acv + write_acv;
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accesses = read_accesses + write_accesses;
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}
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void
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AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
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{
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uint64_t *ipr = xc->regs.ipr;
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// set fault address and flags
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if (!xc->misspeculating() && !xc->regs.intrlock) {
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// set VA register with faulting address
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ipr[AlphaISA::IPR_VA] = vaddr;
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// set MM_STAT register flags
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ipr[AlphaISA::IPR_MM_STAT] = (((OPCODE(xc->getInst()) & 0x3f) << 11)
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| ((RA(xc->getInst()) & 0x1f) << 6)
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| (flags & 0x3f));
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// set VA_FORM register with faulting formatted address
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ipr[AlphaISA::IPR_VA_FORM] =
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ipr[AlphaISA::IPR_MVPTBR] | (VA_VPN(vaddr) << 3);
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// lock these registers until the VA register is read
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xc->regs.intrlock = true;
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}
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}
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Fault
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AlphaDTB::translate(MemReqPtr &req, bool write) const
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{
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RegFile *regs = &req->xc->regs;
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Addr pc = regs->pc;
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InternalProcReg *ipr = regs->ipr;
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AlphaISA::mode_type mode =
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(AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]);
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if (PC_PAL(pc)) {
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mode = (req->flags & ALTMODE) ?
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(AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE])
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: AlphaISA::mode_kernel;
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}
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if (req->flags & PHYSICAL) {
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req->paddr = req->vaddr;
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} else {
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// verify that this is a good virtual address
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if (!validVirtualAddress(req->vaddr)) {
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fault(req->vaddr,
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((write ? MM_STAT_WR_MASK : 0) | MM_STAT_BAD_VA_MASK |
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MM_STAT_ACV_MASK),
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req->xc);
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if (write) { write_acv++; } else { read_acv++; }
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return DTB_Fault_Fault;
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}
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// Check for "superpage" mapping: when SP<1> is set, and
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13>.
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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VA_SPACE(req->vaddr) == 2) {
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// only valid in kernel mode
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if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
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AlphaISA::mode_kernel) {
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fault(req->vaddr,
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((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK),
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req->xc);
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if (write) { write_acv++; } else { read_acv++; }
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return DTB_Acv_Fault;
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}
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req->paddr = req->vaddr & PA_IMPL_MASK;
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} else {
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if (write)
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write_accesses++;
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else
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read_accesses++;
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// not a physical address: need to look up pte
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AlphaISA::PTE *pte = lookup(VA_VPN(req->vaddr),
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DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
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if (!pte) {
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// page fault
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fault(req->vaddr,
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((write ? MM_STAT_WR_MASK : 0) | MM_STAT_DTB_MISS_MASK),
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req->xc);
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if (write) { write_misses++; } else { read_misses++; }
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return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault;
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}
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req->paddr = PA_PFN2PA(pte->ppn) | VA_POFS(req->vaddr);
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if (write) {
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if (!(pte->xwe & MODE2MASK(mode))) {
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// declare the instruction access fault
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fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_ACV_MASK |
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(pte->fonw ? MM_STAT_FONW_MASK : 0),
|
|
req->xc);
|
|
write_acv++;
|
|
return DTB_Fault_Fault;
|
|
}
|
|
if (pte->fonw) {
|
|
fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK,
|
|
req->xc);
|
|
write_acv++;
|
|
return DTB_Fault_Fault;
|
|
}
|
|
} else {
|
|
if (!(pte->xre & MODE2MASK(mode))) {
|
|
fault(req->vaddr,
|
|
MM_STAT_ACV_MASK |
|
|
(pte->fonr ? MM_STAT_FONR_MASK : 0),
|
|
req->xc);
|
|
read_acv++;
|
|
return DTB_Acv_Fault;
|
|
}
|
|
if (pte->fonr) {
|
|
fault(req->vaddr, MM_STAT_FONR_MASK, req->xc);
|
|
read_acv++;
|
|
return DTB_Fault_Fault;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (write)
|
|
write_hits++;
|
|
else
|
|
read_hits++;
|
|
}
|
|
|
|
// check that the physical address is ok (catch bad physical addresses)
|
|
if (req->paddr & ~PA_IMPL_MASK)
|
|
return Machine_Check_Fault;
|
|
|
|
checkCacheability(req);
|
|
|
|
return No_Fault;
|
|
}
|
|
|
|
AlphaISA::PTE &
|
|
AlphaTLB::index(bool advance)
|
|
{
|
|
AlphaISA::PTE *pte = &table[nlu];
|
|
|
|
if (advance)
|
|
nextnlu();
|
|
|
|
return *pte;
|
|
}
|
|
|
|
DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", AlphaTLB)
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
Param<int> size;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
INIT_PARAM_DFLT(size, "TLB size", 48)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
|
|
|
|
|
|
CREATE_SIM_OBJECT(AlphaITB)
|
|
{
|
|
return new AlphaITB(getInstanceName(), size);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
|
|
|
|
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
Param<int> size;
|
|
|
|
END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
INIT_PARAM_DFLT(size, "TLB size", 64)
|
|
|
|
END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
|
|
|
|
|
|
CREATE_SIM_OBJECT(AlphaDTB)
|
|
{
|
|
return new AlphaDTB(getInstanceName(), size);
|
|
}
|
|
|
|
REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
|
|
|