7ac38849ab
this patch removes the GPUStaticInst enums that were defined in GPU.py. instead, a simple set of attribute flags that can be set in the base instruction class are used. this will help unify the attributes of HSAIL and machine ISA instructions within the model itself. because the static instrution now carries the attributes, a GPUDynInst must carry a pointer to a valid GPUStaticInst so a new static kernel launch instruction is added, which carries the attributes needed to perform a the kernel launch.
649 lines
24 KiB
C++
649 lines
24 KiB
C++
/*
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* Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Steve Reinhardt
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*/
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#include "gpu-compute/hsail_code.hh"
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// defined in code.cc, but not worth sucking in all of code.h for this
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// at this point
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extern const char *segmentNames[];
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namespace HsailISA
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{
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template<typename DestDataType, typename AddrRegOperandType>
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void
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LdaInst<DestDataType, AddrRegOperandType>::generateDisassembly()
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{
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this->disassembly = csprintf("%s_%s %s,%s", this->opcode,
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DestDataType::label,
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this->dest.disassemble(),
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this->addr.disassemble());
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}
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template<typename DestDataType, typename AddrRegOperandType>
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void
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LdaInst<DestDataType, AddrRegOperandType>::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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typedef typename DestDataType::CType CType M5_VAR_USED;
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const VectorMask &mask = w->getPred();
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std::vector<Addr> addr_vec;
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addr_vec.resize(w->computeUnit->wfSize(), (Addr)0);
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this->addr.calcVector(w, addr_vec);
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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this->dest.set(w, lane, addr_vec[lane]);
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}
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}
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addr_vec.clear();
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}
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template<typename MemDataType, typename DestDataType,
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typename AddrRegOperandType>
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void
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LdInst<MemDataType, DestDataType, AddrRegOperandType>::generateDisassembly()
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{
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switch (num_dest_operands) {
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case 1:
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this->disassembly = csprintf("%s_%s_%s %s,%s", this->opcode,
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segmentNames[this->segment],
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MemDataType::label,
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this->dest.disassemble(),
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this->addr.disassemble());
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break;
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case 2:
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this->disassembly = csprintf("%s_%s_%s (%s,%s), %s", this->opcode,
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segmentNames[this->segment],
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MemDataType::label,
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this->dest_vect[0].disassemble(),
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this->dest_vect[1].disassemble(),
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this->addr.disassemble());
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break;
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case 3:
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this->disassembly = csprintf("%s_%s_%s (%s,%s,%s), %s", this->opcode,
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segmentNames[this->segment],
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MemDataType::label,
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this->dest_vect[0].disassemble(),
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this->dest_vect[1].disassemble(),
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this->dest_vect[2].disassemble(),
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this->addr.disassemble());
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break;
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case 4:
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this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s",
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this->opcode,
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segmentNames[this->segment],
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MemDataType::label,
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this->dest_vect[0].disassemble(),
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this->dest_vect[1].disassemble(),
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this->dest_vect[2].disassemble(),
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this->dest_vect[3].disassemble(),
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this->addr.disassemble());
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break;
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default:
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fatal("Bad ld register dest operand, num vector operands: %d \n",
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num_dest_operands);
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break;
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}
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}
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static Addr
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calcPrivAddr(Addr addr, Wavefront *w, int lane, GPUStaticInst *i)
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{
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// what is the size of the object we are accessing??
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// NOTE: the compiler doesn't generate enough information
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// to do this yet..have to just line up all the private
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// work-item spaces back to back for now
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/*
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StorageElement* se =
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i->parent->findSymbol(Brig::BrigPrivateSpace, addr);
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assert(se);
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return w->wfSlotId * w->privSizePerItem * w->computeUnit->wfSize() +
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se->offset * w->computeUnit->wfSize() +
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lane * se->size;
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*/
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// addressing strategy: interleave the private spaces of
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// work-items in a wave-front on 8 byte granularity.
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// this won't be perfect coalescing like the spill space
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// strategy, but it's better than nothing. The spill space
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// strategy won't work with private because the same address
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// may be accessed by different sized loads/stores.
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// Note: I'm assuming that the largest load/store to private
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// is 8 bytes. If it is larger, the stride will have to increase
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Addr addr_div8 = addr / 8;
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Addr addr_mod8 = addr % 8;
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Addr ret = addr_div8 * 8 * w->computeUnit->wfSize() + lane * 8 +
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addr_mod8 + w->privBase;
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assert(ret < w->privBase +
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(w->privSizePerItem * w->computeUnit->wfSize()));
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return ret;
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}
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template<typename MemDataType, typename DestDataType,
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typename AddrRegOperandType>
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void
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LdInst<MemDataType, DestDataType,
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AddrRegOperandType>::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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typedef typename MemDataType::CType MemCType;
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const VectorMask &mask = w->getPred();
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// Kernarg references are handled uniquely for now (no Memory Request
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// is used), so special-case them up front. Someday we should
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// make this more realistic, at which we should get rid of this
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// block and fold this case into the switch below.
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if (this->segment == Brig::BRIG_SEGMENT_KERNARG) {
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MemCType val;
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// I assume no vector ld for kernargs
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assert(num_dest_operands == 1);
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// assuming for the moment that we'll never do register
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// offsets into kernarg space... just to make life simpler
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uint64_t address = this->addr.calcUniform();
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val = *(MemCType*)&w->kernelArgs[address];
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DPRINTF(HSAIL, "ld_kernarg [%d] -> %d\n", address, val);
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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this->dest.set(w, lane, val);
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}
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}
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return;
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} else if (this->segment == Brig::BRIG_SEGMENT_ARG) {
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uint64_t address = this->addr.calcUniform();
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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MemCType val = w->readCallArgMem<MemCType>(lane, address);
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DPRINTF(HSAIL, "ld_arg [%d] -> %llu\n", address,
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(unsigned long long)val);
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this->dest.set(w, lane, val);
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}
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}
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return;
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}
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GPUDynInstPtr m = gpuDynInst;
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this->addr.calcVector(w, m->addr);
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m->m_type = MemDataType::memType;
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m->v_type = DestDataType::vgprType;
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m->exec_mask = w->execMask();
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m->statusBitVector = 0;
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m->equiv = this->equivClass;
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if (num_dest_operands == 1) {
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m->dst_reg = this->dest.regIndex();
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m->n_reg = 1;
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} else {
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m->n_reg = num_dest_operands;
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for (int i = 0; i < num_dest_operands; ++i) {
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m->dst_reg_vec[i] = this->dest_vect[i].regIndex();
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}
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}
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m->simdId = w->simdId;
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m->wfSlotId = w->wfSlotId;
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m->wfDynId = w->wfDynId;
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m->kern_id = w->kernId;
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m->cu_id = w->computeUnit->cu_id;
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m->latency.init(&w->computeUnit->shader->tick_cnt);
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switch (this->segment) {
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case Brig::BRIG_SEGMENT_GLOBAL:
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m->pipeId = GLBMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(1));
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// this is a complete hack to get around a compiler bug
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// (the compiler currently generates global access for private
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// addresses (starting from 0). We need to add the private offset)
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (m->addr[lane] < w->privSizePerItem) {
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if (mask[lane]) {
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// what is the size of the object we are accessing?
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// find base for for this wavefront
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// calcPrivAddr will fail if accesses are unaligned
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assert(!((sizeof(MemCType) - 1) & m->addr[lane]));
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Addr privAddr = calcPrivAddr(m->addr[lane], w, lane,
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this);
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m->addr[lane] = privAddr;
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}
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}
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}
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w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
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w->outstandingReqsRdGm++;
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w->rdGmReqsInPipe--;
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break;
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case Brig::BRIG_SEGMENT_SPILL:
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assert(num_dest_operands == 1);
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m->pipeId = GLBMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(1));
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{
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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// note: this calculation will NOT WORK if the compiler
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// ever generates loads/stores to the same address with
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// different widths (e.g., a ld_u32 addr and a ld_u16 addr)
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if (mask[lane]) {
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assert(m->addr[lane] < w->spillSizePerItem);
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m->addr[lane] = m->addr[lane] * w->spillWidth +
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lane * sizeof(MemCType) + w->spillBase;
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w->lastAddr[lane] = m->addr[lane];
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}
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}
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}
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w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
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w->outstandingReqsRdGm++;
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w->rdGmReqsInPipe--;
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break;
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case Brig::BRIG_SEGMENT_GROUP:
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m->pipeId = LDSMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(24));
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w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
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w->outstandingReqsRdLm++;
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w->rdLmReqsInPipe--;
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break;
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case Brig::BRIG_SEGMENT_READONLY:
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m->pipeId = GLBMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(1));
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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assert(m->addr[lane] + sizeof(MemCType) <= w->roSize);
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m->addr[lane] += w->roBase;
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}
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}
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w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
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w->outstandingReqsRdGm++;
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w->rdGmReqsInPipe--;
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break;
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case Brig::BRIG_SEGMENT_PRIVATE:
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m->pipeId = GLBMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(1));
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{
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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assert(m->addr[lane] < w->privSizePerItem);
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m->addr[lane] = m->addr[lane] +
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lane * sizeof(MemCType) + w->privBase;
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}
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}
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}
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w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
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w->outstandingReqsRdGm++;
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w->rdGmReqsInPipe--;
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break;
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default:
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fatal("Load to unsupported segment %d %llxe\n", this->segment,
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m->addr[0]);
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}
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w->outstandingReqs++;
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w->memReqsInPipe--;
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}
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template<typename OperationType, typename SrcDataType,
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typename AddrRegOperandType>
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void
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StInst<OperationType, SrcDataType,
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AddrRegOperandType>::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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typedef typename OperationType::CType CType;
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const VectorMask &mask = w->getPred();
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// arg references are handled uniquely for now (no Memory Request
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// is used), so special-case them up front. Someday we should
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// make this more realistic, at which we should get rid of this
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// block and fold this case into the switch below.
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if (this->segment == Brig::BRIG_SEGMENT_ARG) {
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uint64_t address = this->addr.calcUniform();
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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CType data = this->src.template get<CType>(w, lane);
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DPRINTF(HSAIL, "st_arg [%d] <- %d\n", address, data);
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w->writeCallArgMem<CType>(lane, address, data);
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}
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}
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return;
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}
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GPUDynInstPtr m = gpuDynInst;
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m->exec_mask = w->execMask();
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this->addr.calcVector(w, m->addr);
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if (num_src_operands == 1) {
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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((CType*)m->d_data)[lane] =
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this->src.template get<CType>(w, lane);
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}
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}
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} else {
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for (int k= 0; k < num_src_operands; ++k) {
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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((CType*)m->d_data)[k * w->computeUnit->wfSize() + lane] =
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this->src_vect[k].template get<CType>(w, lane);
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}
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}
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}
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}
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m->m_type = OperationType::memType;
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m->v_type = OperationType::vgprType;
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m->statusBitVector = 0;
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m->equiv = this->equivClass;
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if (num_src_operands == 1) {
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m->n_reg = 1;
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} else {
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m->n_reg = num_src_operands;
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}
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m->simdId = w->simdId;
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m->wfSlotId = w->wfSlotId;
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m->wfDynId = w->wfDynId;
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m->kern_id = w->kernId;
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m->cu_id = w->computeUnit->cu_id;
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m->latency.init(&w->computeUnit->shader->tick_cnt);
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switch (this->segment) {
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case Brig::BRIG_SEGMENT_GLOBAL:
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m->pipeId = GLBMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(1));
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// this is a complete hack to get around a compiler bug
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// (the compiler currently generates global access for private
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// addresses (starting from 0). We need to add the private offset)
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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if (m->addr[lane] < w->privSizePerItem) {
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// calcPrivAddr will fail if accesses are unaligned
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assert(!((sizeof(CType)-1) & m->addr[lane]));
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Addr privAddr = calcPrivAddr(m->addr[lane], w, lane,
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this);
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m->addr[lane] = privAddr;
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}
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}
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}
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w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
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w->outstandingReqsWrGm++;
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w->wrGmReqsInPipe--;
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break;
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case Brig::BRIG_SEGMENT_SPILL:
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assert(num_src_operands == 1);
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m->pipeId = GLBMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(1));
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{
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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assert(m->addr[lane] < w->spillSizePerItem);
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m->addr[lane] = m->addr[lane] * w->spillWidth +
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lane * sizeof(CType) + w->spillBase;
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}
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}
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}
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w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
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w->outstandingReqsWrGm++;
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w->wrGmReqsInPipe--;
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break;
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case Brig::BRIG_SEGMENT_GROUP:
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m->pipeId = LDSMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(24));
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w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
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w->outstandingReqsWrLm++;
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w->wrLmReqsInPipe--;
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break;
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case Brig::BRIG_SEGMENT_PRIVATE:
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m->pipeId = GLBMEM_PIPE;
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m->latency.set(w->computeUnit->shader->ticks(1));
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{
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for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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if (mask[lane]) {
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assert(m->addr[lane] < w->privSizePerItem);
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m->addr[lane] = m->addr[lane] + lane *
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sizeof(CType)+w->privBase;
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}
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}
|
|
}
|
|
|
|
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
|
|
w->outstandingReqsWrGm++;
|
|
w->wrGmReqsInPipe--;
|
|
break;
|
|
|
|
default:
|
|
fatal("Store to unsupported segment %d\n", this->segment);
|
|
}
|
|
|
|
w->outstandingReqs++;
|
|
w->memReqsInPipe--;
|
|
}
|
|
|
|
template<typename OperationType, typename SrcDataType,
|
|
typename AddrRegOperandType>
|
|
void
|
|
StInst<OperationType, SrcDataType,
|
|
AddrRegOperandType>::generateDisassembly()
|
|
{
|
|
switch (num_src_operands) {
|
|
case 1:
|
|
this->disassembly = csprintf("%s_%s_%s %s,%s", this->opcode,
|
|
segmentNames[this->segment],
|
|
OperationType::label,
|
|
this->src.disassemble(),
|
|
this->addr.disassemble());
|
|
break;
|
|
case 2:
|
|
this->disassembly = csprintf("%s_%s_%s (%s,%s), %s", this->opcode,
|
|
segmentNames[this->segment],
|
|
OperationType::label,
|
|
this->src_vect[0].disassemble(),
|
|
this->src_vect[1].disassemble(),
|
|
this->addr.disassemble());
|
|
break;
|
|
case 4:
|
|
this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s",
|
|
this->opcode,
|
|
segmentNames[this->segment],
|
|
OperationType::label,
|
|
this->src_vect[0].disassemble(),
|
|
this->src_vect[1].disassemble(),
|
|
this->src_vect[2].disassemble(),
|
|
this->src_vect[3].disassemble(),
|
|
this->addr.disassemble());
|
|
break;
|
|
default: fatal("Bad ld register src operand, num vector operands: "
|
|
"%d \n", num_src_operands);
|
|
break;
|
|
}
|
|
}
|
|
|
|
template<typename DataType, typename AddrRegOperandType, int NumSrcOperands,
|
|
bool HasDst>
|
|
void
|
|
AtomicInst<DataType, AddrRegOperandType, NumSrcOperands,
|
|
HasDst>::execute(GPUDynInstPtr gpuDynInst)
|
|
{
|
|
typedef typename DataType::CType CType;
|
|
|
|
Wavefront *w = gpuDynInst->wavefront();
|
|
|
|
GPUDynInstPtr m = gpuDynInst;
|
|
|
|
this->addr.calcVector(w, m->addr);
|
|
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
((CType *)m->a_data)[lane] =
|
|
this->src[0].template get<CType>(w, lane);
|
|
}
|
|
|
|
// load second source operand for CAS
|
|
if (NumSrcOperands > 1) {
|
|
for (int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
|
|
((CType*)m->x_data)[lane] =
|
|
this->src[1].template get<CType>(w, lane);
|
|
}
|
|
}
|
|
|
|
assert(NumSrcOperands <= 2);
|
|
|
|
m->m_type = DataType::memType;
|
|
m->v_type = DataType::vgprType;
|
|
|
|
m->exec_mask = w->execMask();
|
|
m->statusBitVector = 0;
|
|
m->equiv = 0; // atomics don't have an equivalence class operand
|
|
m->n_reg = 1;
|
|
|
|
if (HasDst) {
|
|
m->dst_reg = this->dest.regIndex();
|
|
}
|
|
|
|
m->simdId = w->simdId;
|
|
m->wfSlotId = w->wfSlotId;
|
|
m->wfDynId = w->wfDynId;
|
|
m->kern_id = w->kernId;
|
|
m->cu_id = w->computeUnit->cu_id;
|
|
m->latency.init(&w->computeUnit->shader->tick_cnt);
|
|
|
|
switch (this->segment) {
|
|
case Brig::BRIG_SEGMENT_GLOBAL:
|
|
m->latency.set(w->computeUnit->shader->ticks(64));
|
|
m->pipeId = GLBMEM_PIPE;
|
|
|
|
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
|
|
w->outstandingReqsWrGm++;
|
|
w->wrGmReqsInPipe--;
|
|
w->outstandingReqsRdGm++;
|
|
w->rdGmReqsInPipe--;
|
|
break;
|
|
|
|
case Brig::BRIG_SEGMENT_GROUP:
|
|
m->pipeId = LDSMEM_PIPE;
|
|
m->latency.set(w->computeUnit->shader->ticks(24));
|
|
w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
|
|
w->outstandingReqsWrLm++;
|
|
w->wrLmReqsInPipe--;
|
|
w->outstandingReqsRdLm++;
|
|
w->rdLmReqsInPipe--;
|
|
break;
|
|
|
|
default:
|
|
fatal("Atomic op to unsupported segment %d\n",
|
|
this->segment);
|
|
}
|
|
|
|
w->outstandingReqs++;
|
|
w->memReqsInPipe--;
|
|
}
|
|
|
|
const char* atomicOpToString(Brig::BrigAtomicOperation atomicOp);
|
|
|
|
template<typename DataType, typename AddrRegOperandType, int NumSrcOperands,
|
|
bool HasDst>
|
|
void
|
|
AtomicInst<DataType, AddrRegOperandType, NumSrcOperands,
|
|
HasDst>::generateDisassembly()
|
|
{
|
|
if (HasDst) {
|
|
this->disassembly =
|
|
csprintf("%s_%s_%s_%s %s,%s", this->opcode,
|
|
atomicOpToString(this->atomicOperation),
|
|
segmentNames[this->segment],
|
|
DataType::label, this->dest.disassemble(),
|
|
this->addr.disassemble());
|
|
} else {
|
|
this->disassembly =
|
|
csprintf("%s_%s_%s_%s %s", this->opcode,
|
|
atomicOpToString(this->atomicOperation),
|
|
segmentNames[this->segment],
|
|
DataType::label, this->addr.disassemble());
|
|
}
|
|
|
|
for (int i = 0; i < NumSrcOperands; ++i) {
|
|
this->disassembly += ",";
|
|
this->disassembly += this->src[i].disassemble();
|
|
}
|
|
}
|
|
} // namespace HsailISA
|