7ac38849ab
this patch removes the GPUStaticInst enums that were defined in GPU.py. instead, a simple set of attribute flags that can be set in the base instruction class are used. this will help unify the attributes of HSAIL and machine ISA instructions within the model itself. because the static instrution now carries the attributes, a GPUDynInst must carry a pointer to a valid GPUStaticInst so a new static kernel launch instruction is added, which carries the attributes needed to perform a the kernel launch.
439 lines
15 KiB
C++
439 lines
15 KiB
C++
/*
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* Copyright (c) 2012-2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Steve Reinhardt
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*/
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#ifndef __ARCH_HSAIL_INSTS_BRANCH_HH__
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#define __ARCH_HSAIL_INSTS_BRANCH_HH__
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#include "arch/hsail/insts/gpu_static_inst.hh"
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#include "arch/hsail/operand.hh"
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#include "gpu-compute/gpu_dyn_inst.hh"
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#include "gpu-compute/wavefront.hh"
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namespace HsailISA
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{
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// The main difference between a direct branch and an indirect branch
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// is whether the target is a register or a label, so we can share a
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// lot of code if we template the base implementation on that type.
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template<typename TargetType>
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class BrnInstBase : public HsailGPUStaticInst
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{
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public:
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void generateDisassembly() override;
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Brig::BrigWidth8_t width;
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TargetType target;
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BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: HsailGPUStaticInst(obj, "brn")
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{
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setFlag(Branch);
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setFlag(UnconditionalJump);
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width = ((Brig::BrigInstBr*)ib)->width;
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unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
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target.init(op_offs, obj);
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}
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uint32_t getTargetPc() override { return target.getTarget(0, 0); }
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bool isVectorRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.isVectorRegister();
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}
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bool isCondRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.isCondRegister();
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}
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bool isScalarRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.isScalarRegister();
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}
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bool isSrcOperand(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return true;
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}
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bool isDstOperand(int operandIndex) override {
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return false;
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}
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int getOperandSize(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.opSize();
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}
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int getRegisterIndex(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.regIndex();
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}
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int getNumOperands() override {
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return 1;
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}
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void execute(GPUDynInstPtr gpuDynInst) override;
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};
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template<typename TargetType>
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void
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BrnInstBase<TargetType>::generateDisassembly()
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{
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std::string widthClause;
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if (width != 1) {
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widthClause = csprintf("_width(%d)", width);
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}
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disassembly = csprintf("%s%s %s", opcode, widthClause,
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target.disassemble());
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}
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template<typename TargetType>
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void
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BrnInstBase<TargetType>::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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if (getTargetPc() == w->rpc()) {
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w->popFromReconvergenceStack();
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} else {
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// Rpc and execution mask remain the same
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w->pc(getTargetPc());
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}
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w->discardFetch();
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}
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class BrnDirectInst : public BrnInstBase<LabelOperand>
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{
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public:
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BrnDirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: BrnInstBase<LabelOperand>(ib, obj)
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{
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}
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int numSrcRegOperands() { return 0; }
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int numDstRegOperands() { return 0; }
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};
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class BrnIndirectInst : public BrnInstBase<SRegOperand>
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{
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public:
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BrnIndirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: BrnInstBase<SRegOperand>(ib, obj)
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{
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}
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int numSrcRegOperands() { return target.isVectorRegister(); }
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int numDstRegOperands() { return 0; }
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};
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GPUStaticInst* decodeBrn(const Brig::BrigInstBase *ib,
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const BrigObject *obj);
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template<typename TargetType>
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class CbrInstBase : public HsailGPUStaticInst
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{
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public:
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void generateDisassembly() override;
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Brig::BrigWidth8_t width;
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CRegOperand cond;
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TargetType target;
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CbrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: HsailGPUStaticInst(obj, "cbr")
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{
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setFlag(Branch);
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width = ((Brig::BrigInstBr *)ib)->width;
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unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
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cond.init(op_offs, obj);
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op_offs = obj->getOperandPtr(ib->operands, 1);
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target.init(op_offs, obj);
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}
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uint32_t getTargetPc() override { return target.getTarget(0, 0); }
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void execute(GPUDynInstPtr gpuDynInst) override;
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// Assumption: Target is operand 0, Condition Register is operand 1
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bool isVectorRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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if (!operandIndex)
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return target.isVectorRegister();
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else
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return false;
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}
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bool isCondRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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if (!operandIndex)
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return target.isCondRegister();
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else
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return true;
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}
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bool isScalarRegister(int operandIndex) override {
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assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
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if (!operandIndex)
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return target.isScalarRegister();
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else
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return false;
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}
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bool isSrcOperand(int operandIndex) override {
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assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
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if (operandIndex == 0)
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return true;
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return false;
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}
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// both Condition Register and Target are source operands
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bool isDstOperand(int operandIndex) override {
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return false;
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}
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int getOperandSize(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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if (!operandIndex)
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return target.opSize();
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else
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return 1;
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}
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int getRegisterIndex(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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if (!operandIndex)
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return target.regIndex();
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else
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return -1;
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}
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// Operands = Target, Condition Register
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int getNumOperands() override {
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return 2;
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}
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};
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template<typename TargetType>
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void
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CbrInstBase<TargetType>::generateDisassembly()
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{
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std::string widthClause;
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if (width != 1) {
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widthClause = csprintf("_width(%d)", width);
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}
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disassembly = csprintf("%s%s %s,%s", opcode, widthClause,
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cond.disassemble(), target.disassemble());
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}
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template<typename TargetType>
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void
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CbrInstBase<TargetType>::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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const uint32_t curr_pc = w->pc();
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const uint32_t curr_rpc = w->rpc();
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const VectorMask curr_mask = w->execMask();
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/**
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* TODO: can we move this pop outside the instruction, and
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* into the wavefront?
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*/
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w->popFromReconvergenceStack();
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// immediate post-dominator instruction
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const uint32_t rpc = static_cast<uint32_t>(ipdInstNum());
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if (curr_rpc != rpc) {
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w->pushToReconvergenceStack(rpc, curr_rpc, curr_mask);
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}
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// taken branch
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const uint32_t true_pc = getTargetPc();
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VectorMask true_mask;
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for (unsigned int lane = 0; lane < w->computeUnit->wfSize(); ++lane) {
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true_mask[lane] = cond.get<bool>(w, lane) & curr_mask[lane];
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}
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// not taken branch
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const uint32_t false_pc = curr_pc + 1;
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assert(true_pc != false_pc);
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if (false_pc != rpc && true_mask.count() < curr_mask.count()) {
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VectorMask false_mask = curr_mask & ~true_mask;
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w->pushToReconvergenceStack(false_pc, rpc, false_mask);
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}
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if (true_pc != rpc && true_mask.count()) {
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w->pushToReconvergenceStack(true_pc, rpc, true_mask);
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}
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assert(w->pc() != curr_pc);
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w->discardFetch();
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}
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class CbrDirectInst : public CbrInstBase<LabelOperand>
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{
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public:
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CbrDirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: CbrInstBase<LabelOperand>(ib, obj)
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{
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}
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// the source operand of a conditional branch is a Condition
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// Register which is not stored in the VRF
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// so we do not count it as a source-register operand
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// even though, formally, it is one.
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int numSrcRegOperands() { return 0; }
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int numDstRegOperands() { return 0; }
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};
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class CbrIndirectInst : public CbrInstBase<SRegOperand>
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{
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public:
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CbrIndirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: CbrInstBase<SRegOperand>(ib, obj)
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{
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}
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// one source operand of the conditional indirect branch is a Condition
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// register which is not stored in the VRF so we do not count it
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// as a source-register operand even though, formally, it is one.
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int numSrcRegOperands() { return target.isVectorRegister(); }
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int numDstRegOperands() { return 0; }
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};
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GPUStaticInst* decodeCbr(const Brig::BrigInstBase *ib,
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const BrigObject *obj);
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template<typename TargetType>
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class BrInstBase : public HsailGPUStaticInst
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{
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public:
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void generateDisassembly() override;
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ImmOperand<uint32_t> width;
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TargetType target;
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BrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: HsailGPUStaticInst(obj, "br")
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{
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setFlag(Branch);
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setFlag(UnconditionalJump);
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width.init(((Brig::BrigInstBr *)ib)->width, obj);
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unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
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target.init(op_offs, obj);
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}
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uint32_t getTargetPc() override { return target.getTarget(0, 0); }
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void execute(GPUDynInstPtr gpuDynInst) override;
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bool isVectorRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.isVectorRegister();
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}
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bool isCondRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.isCondRegister();
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}
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bool isScalarRegister(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.isScalarRegister();
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}
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bool isSrcOperand(int operandIndex) override {
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assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
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return true;
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}
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bool isDstOperand(int operandIndex) override { return false; }
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int getOperandSize(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.opSize();
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}
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int getRegisterIndex(int operandIndex) override {
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assert(operandIndex >= 0 && operandIndex < getNumOperands());
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return target.regIndex();
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}
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int getNumOperands() override { return 1; }
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};
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template<typename TargetType>
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void
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BrInstBase<TargetType>::generateDisassembly()
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{
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std::string widthClause;
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if (width.bits != 1) {
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widthClause = csprintf("_width(%d)", width.bits);
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}
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disassembly = csprintf("%s%s %s", opcode, widthClause,
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target.disassemble());
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}
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template<typename TargetType>
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void
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BrInstBase<TargetType>::execute(GPUDynInstPtr gpuDynInst)
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{
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Wavefront *w = gpuDynInst->wavefront();
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if (getTargetPc() == w->rpc()) {
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w->popFromReconvergenceStack();
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} else {
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// Rpc and execution mask remain the same
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w->pc(getTargetPc());
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}
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w->discardFetch();
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}
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class BrDirectInst : public BrInstBase<LabelOperand>
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{
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public:
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BrDirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: BrInstBase<LabelOperand>(ib, obj)
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{
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}
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int numSrcRegOperands() { return 0; }
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int numDstRegOperands() { return 0; }
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};
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class BrIndirectInst : public BrInstBase<SRegOperand>
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{
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public:
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BrIndirectInst(const Brig::BrigInstBase *ib, const BrigObject *obj)
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: BrInstBase<SRegOperand>(ib, obj)
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{
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}
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int numSrcRegOperands() { return target.isVectorRegister(); }
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int numDstRegOperands() { return 0; }
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};
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GPUStaticInst* decodeBr(const Brig::BrigInstBase *ib,
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const BrigObject *obj);
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} // namespace HsailISA
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#endif // __ARCH_HSAIL_INSTS_BRANCH_HH__
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