223 lines
7.4 KiB
C++
223 lines
7.4 KiB
C++
/*
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* Copyright (c) 2014,2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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* Stephen Hines
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*/
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#include "arch/arm/insts/pseudo.hh"
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#include "cpu/exec_context.hh"
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DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
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: ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
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faultId(static_cast<DecoderFault>(
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static_cast<uint8_t>(_machInst.decoderFault)))
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{
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// Don't call execute() if we're on a speculative path and the
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// fault is an internal panic fault.
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flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC);
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}
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Fault
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DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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const PCState pc_state(xc->pcState());
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const Addr pc(pc_state.instAddr());
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switch (faultId) {
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case DecoderFault::UNALIGNED:
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if (machInst.aarch64) {
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return std::make_shared<PCAlignmentFault>(pc);
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} else {
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// TODO: We should check if we the receiving end is in
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// aarch64 mode and raise a PCAlignment fault instead.
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return std::make_shared<PrefetchAbort>(
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pc, ArmFault::AlignmentFault);
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}
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case DecoderFault::PANIC:
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panic("Internal error in instruction decoder\n");
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case DecoderFault::OK:
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panic("Decoder fault instruction without decoder fault.\n");
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}
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panic("Unhandled fault type");
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}
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const char *
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DecoderFaultInst::faultName() const
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{
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switch (faultId) {
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case DecoderFault::OK:
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return "OK";
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case DecoderFault::UNALIGNED:
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return "UnalignedInstruction";
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case DecoderFault::PANIC:
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return "DecoderPanic";
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}
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panic("Unhandled fault type");
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}
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std::string
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DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("gem5fault %s", faultName());
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}
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FailUnimplemented::FailUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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FailUnimplemented::FailUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst,
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const std::string& _fullMnemonic)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass),
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fullMnemonic(_fullMnemonic)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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Fault
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FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
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}
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std::string
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FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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}
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WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
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ExtMachInst _machInst,
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const std::string& _fullMnemonic)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
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fullMnemonic(_fullMnemonic)
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{
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// don't call execute() (which panics) if we're on a
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// speculative path
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flags[IsNonSpeculative] = true;
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}
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Fault
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WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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if (!warned) {
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warn("\tinstruction '%s' unimplemented\n",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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warned = true;
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}
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return NoFault;
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}
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std::string
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WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (unimplemented)",
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fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
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}
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McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
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uint64_t _iss, MiscRegIndex _miscReg)
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: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
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{
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flags[IsNonSpeculative] = true;
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iss = _iss;
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miscReg = _miscReg;
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}
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Fault
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McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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{
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uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
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uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
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uint32_t scr = xc->readMiscReg(MISCREG_SCR);
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uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
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uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
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uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
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bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
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hcptr, iss);
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if (hypTrap) {
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return std::make_shared<HypervisorTrap>(machInst, iss,
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EC_TRAPPED_CP15_MCR_MRC);
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}
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if (miscReg == MISCREG_DCCMVAC)
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return std::make_shared<FlushPipe>();
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else
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return NoFault;
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}
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std::string
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McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (pipe flush)", mnemonic);
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}
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