153 lines
5.4 KiB
C++
153 lines
5.4 KiB
C++
/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_UTILITY_HH__
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#define __ARCH_X86_UTILITY_HH__
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#include "arch/x86/types.hh"
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "sim/host.hh"
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class ThreadContext;
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namespace __hash_namespace {
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template<>
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struct hash<X86ISA::ExtMachInst> {
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size_t operator()(const X86ISA::ExtMachInst &emi) const {
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return (((uint64_t)emi.legacy << 56) |
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((uint64_t)emi.rex << 48) |
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((uint64_t)emi.modRM << 40) |
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((uint64_t)emi.sib << 32) |
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((uint64_t)emi.opcode.num << 24) |
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((uint64_t)emi.opcode.prefixA << 16) |
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((uint64_t)emi.opcode.prefixB << 8) |
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((uint64_t)emi.opcode.op)) ^
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emi.immediate ^ emi.displacement ^
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emi.mode ^
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emi.opSize ^ emi.addrSize ^ emi.stackSize;
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};
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};
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}
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namespace X86ISA
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{
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uint64_t getArgument(ThreadContext *tc, int number, bool fp);
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static inline bool
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inUserMode(ThreadContext *tc)
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{
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return false;
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}
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inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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inline bool isCallerSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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inline bool isCalleeSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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// Instruction address compression hooks
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inline Addr realPCToFetchPC(const Addr &addr)
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{
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return addr;
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}
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inline Addr fetchPCToRealPC(const Addr &addr)
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{
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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inline size_t fetchInstSize()
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{
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return sizeof(MachInst);
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param tc The thread context.
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*/
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template <class TC>
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void zeroRegisters(TC *tc);
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#if FULL_SYSTEM
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void initCPU(ThreadContext *tc, int cpuId);
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#endif
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void startupCPU(ThreadContext *tc, int cpuId);
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};
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#endif // __ARCH_X86_UTILITY_HH__
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