54b47bc5ae
arch/mips/faults.hh: remove nonsense arch/mips/isa/base.isa: define R31 arch/mips/isa/bitfields.isa: forgotten bitfields arch/mips/isa/decoder.isa: INT64 -> int64_t arch/mips/isa/formats.isa: fix comments arch/mips/isa/formats/branch.isa: Branch -> BranchLikely RB -> RT arch/mips/isa/formats/fp.isa: Make FP ops generates arch/mips/isa/formats/mem.isa: RA,RB -> RS,RT arch/mips/isa/formats/noop.isa: Rc -> Rd arch/mips/isa/formats/util.isa: forgot brace and semicolon arch/mips/isa/includes.isa: remove unnecessary files arch/mips/isa_traits.hh: spacing cpu/static_inst.hh: add cond_delay_slot flag --HG-- extra : convert_revision : 3bc7353b437f9a764e85cc462bed86c9d654eb37
317 lines
8.4 KiB
C++
317 lines
8.4 KiB
C++
// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Control transfer instructions
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//
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output header {{
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/**
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* Base class for instructions whose disassembly is not purely a
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* function of the machine instruction (i.e., it depends on the
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* PC). This class overrides the disassemble() method to check
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* the PC and symbol table values before re-using a cached
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* disassembly string. This is necessary for branches and jumps,
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* where the disassembly string includes the target address (which
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* may depend on the PC and/or symbol table).
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*/
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class PCDependentDisassembly : public MipsStaticInst
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{
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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/// Cached symbol table pointer from last disassembly
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mutable const SymbolTable *cachedSymtab;
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/// Constructor
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PCDependentDisassembly(const char *mnem, MachInst _machInst,
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OpClass __opClass)
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: MipsStaticInst(mnem, _machInst, __opClass),
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cachedPC(0), cachedSymtab(0)
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{
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}
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const std::string &
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disassemble(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for branches (PC-relative control transfers),
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* conditional or unconditional.
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*/
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class Branch : public PCDependentDisassembly
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{
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protected:
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/// target address (signed) Displacement .
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int32_t disp;
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/// Constructor.
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(OFFSET << 2)
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{
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}
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Addr branchTarget(Addr branchPC) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for branch likely branches (PC-relative control transfers),
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*/
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class BranchLikely : public PCDependentDisassembly
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{
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protected:
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/// target address (signed) Displacement .
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int32_t disp;
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/// Constructor.
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BranchLikely(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(OFFSET << 2)
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{
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}
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Addr branchTarget(Addr branchPC) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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/**
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* Base class for jumps (register-indirect control transfers). In
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* the Mips ISA, these are always unconditional.
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*/
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class Jump : public PCDependentDisassembly
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{
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protected:
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/// Displacement to target address (signed).
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int32_t disp;
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public:
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/// Constructor
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Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
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: PCDependentDisassembly(mnem, _machInst, __opClass),
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disp(OFFSET)
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{
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}
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Addr branchTarget(ExecContext *xc) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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Addr
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Branch::branchTarget(Addr branchPC) const
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{
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return branchPC + 4 + disp;
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}
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Addr
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BranchLikely::branchTarget(Addr branchPC) const
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{
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return branchPC + 4 + disp;
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}
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Addr
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Jump::branchTarget(ExecContext *xc) const
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{
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Addr NPC = xc->readPC() + 4;
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uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
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return (Rb & ~3) | (NPC & 1);
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}
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const std::string &
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PCDependentDisassembly::disassemble(Addr pc,
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const SymbolTable *symtab) const
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{
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if (!cachedDisassembly ||
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pc != cachedPC || symtab != cachedSymtab)
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{
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if (cachedDisassembly)
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delete cachedDisassembly;
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cachedDisassembly =
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new std::string(generateDisassembly(pc, symtab));
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cachedPC = pc;
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cachedSymtab = symtab;
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}
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return *cachedDisassembly;
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}
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std::string
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Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// There's only one register arg (RA), but it could be
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// either a source (the condition for conditional
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// branches) or a destination (the link reg for
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// unconditional branches)
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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ss << ",";
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}
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else if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ",";
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}
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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if (_numSrcRegs == 0 && _numDestRegs == 0) {
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printReg(ss, 31);
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ss << ",";
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}
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#endif
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Addr target = pc + 4 + disp;
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std::string str;
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if (symtab && symtab->findSymbol(target, str))
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ss << str;
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else
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ccprintf(ss, "0x%x", target);
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return ss.str();
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}
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std::string
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BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// There's only one register arg (RA), but it could be
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// either a source (the condition for conditional
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// branches) or a destination (the link reg for
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// unconditional branches)
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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ss << ",";
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}
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else if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ",";
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}
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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if (_numSrcRegs == 0 && _numDestRegs == 0) {
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printReg(ss, 31);
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ss << ",";
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}
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#endif
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Addr target = pc + 4 + disp;
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std::string str;
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if (symtab && symtab->findSymbol(target, str))
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ss << str;
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else
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ccprintf(ss, "0x%x", target);
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return ss.str();
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}
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std::string
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Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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if (_numDestRegs == 0) {
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printReg(ss, 31);
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ss << ",";
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}
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#endif
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if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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ss << ",";
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}
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ccprintf(ss, "(r%d)", RT);
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return ss.str();
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}
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}};
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def format Branch(code,*flags) {{
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#Add Link Code if Link instruction
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strlen = len(name)
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if name[strlen-2:] == 'al':
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code += 'R31 = NNPC;\n'
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#Condition code
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code = 'bool cond;\n' + code
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code += 'if (cond) {\n'
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#code += '//NPC=NPC: just placeholder to force parser to writeback NPC\n'
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#code += ' NPC = NPC; \n'
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code += ' NNPC = NPC + disp;\n'
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code += '} \n'
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iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
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('IsDirectControl', 'IsCondControl'))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format BranchLikely(code,*flags) {{
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#Add Link Code if Link instruction
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strlen = len(name)
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if name[strlen-3:] == 'all':
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code += 'R31 = NNPC;\n'
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#Condition code
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code = 'bool cond;\n' + code
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code += 'if (cond) {'
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#code += '//NPC=NPC: just placeholder to force parser to writeback NPC\n'
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#code += 'NPC = NPC; \n'
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code += 'NNPC = NPC + disp;\n'
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code += '} \n'
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iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
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('IsDirectControl', 'IsCondControl','IsCondDelaySlot'))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def format Jump(code,*flags) {{
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#Add Link Code if Link instruction
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strlen = len(name)
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if strlen >= 3 and name[2:3] == 'al':
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code = 'R31 = NNPC;\n' + code
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iop = InstObjParams(name, Name, 'Jump', CodeBlock(code),\
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('IsIndirectControl', 'IsUncondControl'))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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