7a2ecf9e26
util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha --HG-- rename : util/m5/Makefile => util/m5/Makefile.sparc rename : util/m5/m5op.S => util/m5/m5op_alpha.S extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
162 lines
8.4 KiB
Plaintext
162 lines
8.4 KiB
Plaintext
// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Ali Saidi
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// Gabe Black
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// Steve Reinhardt
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def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'shw' : ('signed int', 16),
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'uhw' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sdw' : ('signed int', 64),
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'udw' : ('unsigned int', 64),
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'tudw' : ('twin int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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output header {{
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// A function to "decompress" double and quad floating point
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// register numbers stuffed into 5 bit fields. These have their
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// MSB put in the LSB position but are otherwise normal.
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static inline unsigned int dfpr(unsigned int regNum)
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{
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return (regNum & (~1)) | ((regNum & 1) << 5);
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}
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}};
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def operands {{
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# Int regs default to unsigned, but code should not count on this.
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# For clarity, descriptions that depend on unsigned behavior should
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# explicitly specify '.uq'.
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'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
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# The Rd from the previous window
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'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
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# The Rd from the next window
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'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
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# For microcoded twin load instructions, RdTwin appears in the "code"
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# for the instruction is replaced by RdLow or RdHigh by the format
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# before it's processed by the iop.
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# The low (even) register of a two register pair
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'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
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# The high (odd) register of a two register pair
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'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
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'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
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'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
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# A microcode register. Right now, this is the only one.
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'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
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# Because double and quad precision register numbers are decoded
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# differently, they get different operands. The single precision versions
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# have an s post pended to their name.
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'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
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'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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# Each Frd_N refers to the Nth double precision register from Frd.
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# Note that this adds twice N to the register number.
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'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
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'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
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'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
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'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
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'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
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'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
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'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
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'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
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'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
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'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
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'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
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'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
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# Registers which are used explicitly in instructions
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'R0': ('IntReg', 'udw', '0', None, 6),
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'R1': ('IntReg', 'udw', '1', None, 7),
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'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
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'R16': ('IntReg', 'udw', '16', None, 9),
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'O0': ('IntReg', 'udw', '24', 'IsInteger', 10),
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'O1': ('IntReg', 'udw', '25', 'IsInteger', 11),
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'O2': ('IntReg', 'udw', '26', 'IsInteger', 12),
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'O3': ('IntReg', 'udw', '27', 'IsInteger', 13),
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'O4': ('IntReg', 'udw', '28', 'IsInteger', 14),
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'O5': ('IntReg', 'udw', '29', 'IsInteger', 15),
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# Control registers
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# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
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# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
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'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
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'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
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'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
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'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
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'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
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'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
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'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
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'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
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'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
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'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
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'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
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'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
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'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
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'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
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'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
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'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
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'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
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'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
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'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
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'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
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'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
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'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
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# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
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# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
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# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
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# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
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# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
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'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
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'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
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'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
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'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
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'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
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'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
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'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
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'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
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'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
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'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
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'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
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'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
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'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
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'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
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# Mem gets a large number so it's always last
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'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
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}};
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