7a2ecf9e26
util/m5/Makefile.alpha:
Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
Make the makefile more reasonable
util/m5/Makefile.alpha:
Remove authors from copyright.
util/m5/Makefile.alpha:
Updated Authors from bk prs info
util/m5/Makefile.alpha:
bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
ivle and ivlb aren't used anymore
util/m5/m5op.h:
stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
move the op ids into their own header file since we can share them between sparc and alpha
--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834
84 lines
3.1 KiB
Plaintext
84 lines
3.1 KiB
Plaintext
// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Ali Saidi
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// Gabe Black
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// Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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// Bitfields are shared liberally between instruction formats, so they are
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// simply defined alphabetically
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def bitfield A <29>;
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def bitfield BPCC <21:20>; // for BPcc & FBPcc
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def bitfield FCMPCC <26:25>; // for FCMP & FCMPEa
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def bitfield FMOVCC <13:11>; // for FMOVcc
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def bitfield CC <12:11>; // for MOVcc & Tcc
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def bitfield MOVCC3 <18>; // also for MOVcc
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def bitfield CMASK <6:4>;
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def bitfield COND2 <28:25>;
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def bitfield COND4 <17:14>;
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def bitfield D16HI <21:20>;
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def bitfield D16LO <13:0>;
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def bitfield DISP19 <18:0>;
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def bitfield DISP22 <21:0>;
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def bitfield DISP30 <29:0>;
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def bitfield FCN <29:25>;
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def bitfield I <13>;
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def bitfield IMM_ASI <12:5>;
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def bitfield IMM22 <21:0>;
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def bitfield M5FUNC <15:7>;
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def bitfield MMASK <3:0>;
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def bitfield OP <31:30>;
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def bitfield OP2 <24:22>;
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def bitfield OP3 <24:19>;
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def bitfield OPF <13:5>;
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def bitfield OPF_CC <13:11>;
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def bitfield OPF_LOW5 <9:5>;
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def bitfield OPF_LOW6 <10:5>;
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def bitfield P <19>;
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def bitfield RCOND2 <27:25>;
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def bitfield RCOND3 <12:10>;
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def bitfield RCOND4 <12:10>;
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def bitfield RD <29:25>;
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def bitfield RS1 <18:14>;
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def bitfield RS2 <4:0>;
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def bitfield SHCNT32 <4:0>;
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def bitfield SHCNT64 <5:0>;
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def bitfield SIMM10 <9:0>;
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def bitfield SIMM11 <10:0>;
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def bitfield SIMM13 <12:0>;
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def bitfield SW_TRAP <7:0>;
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def bitfield X <12>;
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// Extended bitfields which aren't part of the actual instruction.
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def bitfield EXT_ASI <39:32>;
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