1e2a455a23
This Python script generates an ARM DS-5 Streamline .apc project based on gem5 run. To successfully convert, the gem5 runs needs to be run with the context-switch-based stats dump option enabled (The guest kernel also needs to be patched to allow gem5 interrogate its task information.) See help for more information.
120 lines
3.7 KiB
INI
120 lines
3.7 KiB
INI
# Copyright (c) 2012 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Dam Sunwoo
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#
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# Sample stats config file (O3CPU) for m5stats2streamline.py
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#
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# Stats grouped together will show as grouped in Streamline.
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# E.g.,
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#
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# icache =
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# icache.overall_hits::total
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# icache.overall_misses::total
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#
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# will display the icache as a stacked line chart.
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# Charts will still be configurable in Streamline.
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[PER_CPU_STATS]
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# "system.cpu#." will automatically prepended for per-CPU stats
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icache =
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icache.overall_hits::total
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icache.overall_misses::total
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dcache =
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dcache.overall_hits::total
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dcache.overall_misses::total
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[PER_SWITCHCPU_STATS]
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# If starting from checkpoints, CPU stats will be kept in system.switch_cpus#.
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# structures.
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# "system.switch_cpus#" will automatically prepended for per-CPU stats.
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# Note: L1 caches and table walker caches will still be connected to
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# system.cpu#!
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commit_inst_count =
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commit.committedInsts
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commit.commitSquashedInsts
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cycles =
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numCycles
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idleCycles
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branch_mispredict =
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commit.branchMispredicts
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itb =
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itb.hits
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itb.misses
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dtb =
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dtb.hits
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dtb.misses
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commit_inst_breakdown =
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commit.loads
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commit.membars
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commit.branches
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commit.fp_insts
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commit.int_insts
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int_regfile =
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int_regfile_reads
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int_regfile_writes
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misc_regfile =
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misc_regfile_reads
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misc_regfile_writes
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rename_full =
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rename.ROBFullEvents
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rename.IQFullEvents
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rename.LSQFullEvents
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[PER_L2_STATS]
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# Automatically adapts to how many l2 caches are in the system
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l2 =
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overall_hits::total
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overall_misses::total
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[OTHER_STATS]
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# Anything that doesn't belong to CPU or L2 caches
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physmem =
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system.physmem.bytes_read::total
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system.physmem.bytes_written::total
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