gem5/src/arch/x86/isa
Gabe Black 798caa36ad Include the new GenFault microop.
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extra : convert_revision : 6c943329525d2a01f35ad5e56ff91505d5011d7b
2007-04-10 17:26:04 +00:00
..
decoder Changed some instruction names to be in all caps, and "implemented" move to test the stub code for instructions. 2007-04-10 17:22:45 +00:00
formats Reworked x86 a bit 2007-04-10 17:25:15 +00:00
microops Include the new GenFault microop. 2007-04-10 17:26:04 +00:00
base.isa Added a class which lets you manipulate all the strings returned by the parser as a unit. 2007-04-10 17:14:51 +00:00
bitfields.isa Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are. 2007-03-21 19:19:53 +00:00
includes.isa A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented. 2007-04-03 15:01:09 +00:00
macroop.isa Reworked x86 a bit 2007-04-10 17:25:15 +00:00
main.isa Move the instruction specialization stuff out of the microassembler file, and added some comments to main.isa 2007-04-06 16:55:56 +00:00
microasm.isa Reworked x86 a bit 2007-04-10 17:25:15 +00:00
operands.isa The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst. 2007-04-04 23:35:20 +00:00
specialize.isa Reworked x86 a bit 2007-04-10 17:25:15 +00:00