gem5/src/arch/x86/x86_traits.hh
Nilay Vaish 6369df59c8 x86: Add a separate register for D flag bit
The D flag bit is part of the cc flag bit register currently. But since it
is not being used any where in the implementation, it creates an unnecessary
dependency. Hence, it is being moved to a separate register.
2012-09-11 09:25:43 -05:00

109 lines
4.2 KiB
C++

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#ifndef __ARCH_X86_X86TRAITS_HH__
#define __ARCH_X86_X86TRAITS_HH__
#include <cassert>
#include "base/types.hh"
namespace X86ISA
{
const int NumMicroIntRegs = 16;
const int NumPseudoIntRegs = 5;
//1. The condition code bits of the rflags register.
const int NumImplicitIntRegs = 6;
//1. The lower part of the result of multiplication.
//2. The upper part of the result of multiplication.
//3. The quotient from division
//4. The remainder from division
//5. The divisor for division
//6. The register to use for shift doubles
const int NumMMXRegs = 8;
const int NumXMMRegs = 16;
const int NumMicroFpRegs = 8;
const int NumCRegs = 16;
const int NumDRegs = 8;
const int NumSegments = 6;
const int NumSysSegments = 4;
const Addr IntAddrPrefixMask = ULL(0xffffffff00000000);
const Addr IntAddrPrefixCPUID = ULL(0x100000000);
const Addr IntAddrPrefixMSR = ULL(0x200000000);
const Addr IntAddrPrefixIO = ULL(0x300000000);
const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000);
const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000);
// Each APIC gets two pages. One page is used for local apics to field
// accesses from the CPU, and the other is for all APICs to communicate.
const Addr PhysAddrAPICRangeSize = 1 << 12;
static inline Addr
x86IOAddress(const uint32_t port)
{
return PhysAddrPrefixIO | port;
}
static inline Addr
x86PciConfigAddress(const uint32_t addr)
{
return PhysAddrPrefixPciConfig | addr;
}
static inline Addr
x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
{
assert(addr < (1 << 12));
return PhysAddrPrefixLocalAPIC | (id * (1 << 12)) | addr;
}
static inline Addr
x86InterruptAddress(const uint8_t id, const uint16_t addr)
{
assert(addr < PhysAddrAPICRangeSize);
return PhysAddrPrefixInterrupts | (id * PhysAddrAPICRangeSize) | addr;
}
}
#endif //__ARCH_X86_X86TRAITS_HH__