300 lines
33 KiB
Text
300 lines
33 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 22440 # Simulator instruction rate (inst/s)
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host_mem_usage 153392 # Number of bytes of host memory used
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host_seconds 0.29 # Real time elapsed on the host
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host_tick_rate 109185606 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 6404 # Number of instructions simulated
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sim_seconds 0.000031 # Number of seconds simulated
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sim_ticks 31194000 # Number of ticks simulated
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system.cpu.AGEN-Unit.agens 2050 # Number of Address Generations
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system.cpu.Branch-Predictor.BTBHitPct 29.967427 # BTB Hit Percentage
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system.cpu.Branch-Predictor.BTBHits 92 # Number of BTB hits
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system.cpu.Branch-Predictor.BTBLookups 307 # Number of BTB lookups
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system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.Branch-Predictor.condIncorrect 529 # Number of conditional branches incorrect
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system.cpu.Branch-Predictor.condPredicted 750 # Number of conditional branches predicted
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system.cpu.Branch-Predictor.lookups 1051 # Number of BP lookups
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system.cpu.Branch-Predictor.predictedNotTaken 817 # Number of Branches Predicted As Not Taken (False).
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system.cpu.Branch-Predictor.predictedTaken 234 # Number of Branches Predicted As Taken (True).
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system.cpu.Branch-Predictor.usedRAS 124 # Number of times the RAS was used to get a target.
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system.cpu.Execution-Unit.executions 4354 # Number of Instructions Executed.
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system.cpu.Execution-Unit.mispredictPct 50.333016 # Percentage of Incorrect Branches Predicts
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system.cpu.Execution-Unit.mispredicted 529 # Number of Branches Incorrectly Predicted
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system.cpu.Execution-Unit.predicted 522 # Number of Branches Incorrectly Predicted
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system.cpu.Execution-Unit.predictedNotTakenIncorrect 523 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.Execution-Unit.predictedTakenIncorrect 6 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
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system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed
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system.cpu.RegFile-Manager.regFileAccesses 12569 # Number of Total Accesses (Read+Write) to the Register File
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system.cpu.RegFile-Manager.regFileReads 7986 # Number of Reads from Register File
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system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File
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system.cpu.RegFile-Manager.regForwards 315 # Number of Registers Read Through Forwarding Logic
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system.cpu.activity 21.904502 # Percentage of cycles cpu is active
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system.cpu.comBranches 1051 # Number of Branches instructions committed
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system.cpu.comFloats 2 # Number of Floating Point instructions committed
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system.cpu.comInts 3265 # Number of Integer instructions committed
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system.cpu.comLoads 1185 # Number of Load instructions committed
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system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
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system.cpu.comNops 17 # Number of Nop instructions committed
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system.cpu.comStores 865 # Number of Store instructions committed
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system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread)
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system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total)
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.cpi 9.742192 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.cpi_total 9.742192 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56384.210526 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53384.210526 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5356500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 5071500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56068.965517 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.965517 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 4878000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 4617000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56233.516484 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 10234500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 9688500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.025297 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 103.617621 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56233.516484 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 1868 # number of overall hits
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system.cpu.dcache.overall_miss_latency 10234500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 182 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 9688500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 103.617621 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dtb.data_accesses 2060 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 2050 # DTB hits
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system.cpu.dtb.data_misses 10 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 1192 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 1185 # DTB read hits
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system.cpu.dtb.read_misses 7 # DTB read misses
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system.cpu.dtb.write_accesses 868 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 865 # DTB write hits
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system.cpu.dtb.write_misses 3 # DTB write misses
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system.cpu.icache.ReadReq_accesses 7169 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 55706.484642 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 52877.192982 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 6876 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 16322000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.040870 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 293 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 15070000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.039754 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 24.211268 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 7169 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 55706.484642 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency
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system.cpu.icache.demand_hits 6876 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.040870 # miss rate for demand accesses
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system.cpu.icache.demand_misses 293 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 15070000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.039754 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.063594 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 130.240724 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 7169 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 55706.484642 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 6876 # number of overall hits
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system.cpu.icache.overall_miss_latency 16322000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.040870 # miss rate for overall accesses
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system.cpu.icache.overall_misses 293 # number of overall misses
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system.cpu.icache.overall_mshr_hits 8 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 15070000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.039754 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 130.240724 # Cycle average of tags in use
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system.cpu.icache.total_refs 6876 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 48723 # Number of cycles cpu's stages were not processed
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system.cpu.ipc 0.102646 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.ipc_total 0.102646 # IPC: Total IPC of All Threads
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.fetch_accesses 7186 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_hits 7169 # ITB hits
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system.cpu.itb.fetch_misses 17 # ITB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 3801500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52085.751979 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39947.229551 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 19740500 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 15140000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52035.714286 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.002747 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52084.070796 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 23542000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 18061000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.997792 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 452 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::0 181.374052 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52084.070796 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 1 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 23542000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses 452 # number of overall misses
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_miss_latency 18061000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997792 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_misses 452 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.tagsinuse 181.374052 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.numCycles 62389 # number of cpu cycles simulated
|
|
system.cpu.runCycles 13666 # Number of cycles cpu stages are processed.
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
|
|
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
|
|
system.cpu.stage-0.idleCycles 55203 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-0.runCycles 7186 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-0.utilization 11.518056 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-1.idleCycles 55836 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-1.runCycles 6553 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-1.utilization 10.503454 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-2.idleCycles 55919 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-2.utilization 10.370418 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-3.idleCycles 60336 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-3.utilization 3.290644 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage-4.idleCycles 55985 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage-4.utilization 10.264630 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.threadCycles 62389 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|