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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
Andreas Hansson 25e1b1c1f5 stats: Update stats for cache, crossbar and DRAM changes 
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.

Needless to say, almost every regression is affected.
2015-07-03 10:15:03 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 1.962608 # Number of seconds simulated
sim_ticks 1962608482500 # Number of ticks simulated
final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1019388 # Simulator instruction rate (inst/s)
host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 32859851956 # Simulator tick rate (ticks/s)
host_mem_usage 375280 # Number of bytes of host memory used
host_seconds 59.73 # Real time elapsed on the host
sim_insts 60884587 # Number of instructions simulated
sim_ops 60884587 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory
system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory
system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 406729 # Number of read requests accepted
system.physmem.writeReqs 120393 # Number of write requests accepted
system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25025 # Per bank write bursts
system.physmem.perBankRdBursts::1 25421 # Per bank write bursts
system.physmem.perBankRdBursts::2 25447 # Per bank write bursts
system.physmem.perBankRdBursts::3 24899 # Per bank write bursts
system.physmem.perBankRdBursts::4 25181 # Per bank write bursts
system.physmem.perBankRdBursts::5 25235 # Per bank write bursts
system.physmem.perBankRdBursts::6 25799 # Per bank write bursts
system.physmem.perBankRdBursts::7 25539 # Per bank write bursts
system.physmem.perBankRdBursts::8 25681 # Per bank write bursts
system.physmem.perBankRdBursts::9 25348 # Per bank write bursts
system.physmem.perBankRdBursts::10 25259 # Per bank write bursts
system.physmem.perBankRdBursts::11 25592 # Per bank write bursts
system.physmem.perBankRdBursts::12 25653 # Per bank write bursts
system.physmem.perBankRdBursts::13 25554 # Per bank write bursts
system.physmem.perBankRdBursts::14 25887 # Per bank write bursts
system.physmem.perBankRdBursts::15 25094 # Per bank write bursts
system.physmem.perBankWrBursts::0 7701 # Per bank write bursts
system.physmem.perBankWrBursts::1 7641 # Per bank write bursts
system.physmem.perBankWrBursts::2 7454 # Per bank write bursts
system.physmem.perBankWrBursts::3 6926 # Per bank write bursts
system.physmem.perBankWrBursts::4 7165 # Per bank write bursts
system.physmem.perBankWrBursts::5 7117 # Per bank write bursts
system.physmem.perBankWrBursts::6 7626 # Per bank write bursts
system.physmem.perBankWrBursts::7 7252 # Per bank write bursts
system.physmem.perBankWrBursts::8 7527 # Per bank write bursts
system.physmem.perBankWrBursts::9 7238 # Per bank write bursts
system.physmem.perBankWrBursts::10 7225 # Per bank write bursts
system.physmem.perBankWrBursts::11 7418 # Per bank write bursts
system.physmem.perBankWrBursts::12 7843 # Per bank write bursts
system.physmem.perBankWrBursts::13 8207 # Per bank write bursts
system.physmem.perBankWrBursts::14 8447 # Per bank write bursts
system.physmem.perBankWrBursts::15 7584 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
system.physmem.totGap 1962561950500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 406729 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 120393 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads
system.physmem.totQLat 2204423500 # Total ticks spent queuing
system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.13 # Data bus utilization in percentage
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing
system.physmem.readRowHits 363741 # Number of row buffer hits during reads
system.physmem.writeRowHits 96228 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes
system.physmem.avgGap 3723164.56 # Average gap between requests
system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.630269 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states
system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.683332 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states
system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.read_hits 7500026 # DTB read hits
system.cpu0.dtb.read_misses 7443 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
system.cpu0.dtb.read_accesses 490673 # DTB read accesses
system.cpu0.dtb.write_hits 5074087 # DTB write hits
system.cpu0.dtb.write_misses 813 # DTB write misses
system.cpu0.dtb.write_acv 134 # DTB write access violations
system.cpu0.dtb.write_accesses 187452 # DTB write accesses
system.cpu0.dtb.data_hits 12574113 # DTB hits
system.cpu0.dtb.data_misses 8256 # DTB misses
system.cpu0.dtb.data_acv 344 # DTB access violations
system.cpu0.dtb.data_accesses 678125 # DTB accesses
system.cpu0.itb.fetch_hits 3504450 # ITB hits
system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
system.cpu0.itb.fetch_accesses 3508321 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.write_acv 0 # DTB write access violations
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.numCycles 3923838721 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 47783493 # Number of instructions committed
system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses
system.cpu0.num_func_calls 1203861 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls
system.cpu0.num_int_insts 44315744 # number of integer instructions
system.cpu0.num_fp_insts 211234 # number of float instructions
system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read
system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written
system.cpu0.num_mem_refs 12614351 # number of memory refs
system.cpu0.num_load_insts 7527207 # Number of load instructions
system.cpu0.num_store_insts 5087144 # Number of store instructions
system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles
system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles
system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles
system.cpu0.Branches 7204257 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction
system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction
system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction
system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction
system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction
system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction
system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 47792093 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed
system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed
system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed
system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed
system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed
system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
system.cpu0.kern.callpal::total 150081 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1282
system.cpu0.kern.mode_good::user 1282
system.cpu0.kern.mode_good::idle 0
system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3073 # number of times the context was actually changed
system.cpu0.dcache.tags.replacements 1181794 # number of replacements
system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits
system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses
system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks
system.cpu0.dcache.writebacks::total 679941 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 700401 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits
system.cpu0.icache.overall_hits::total 47091062 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses
system.cpu0.icache.overall_misses::total 701031 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.read_hits 2409623 # DTB read hits
system.cpu1.dtb.read_misses 2992 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
system.cpu1.dtb.read_accesses 239363 # DTB read accesses
system.cpu1.dtb.write_hits 1749165 # DTB write hits
system.cpu1.dtb.write_misses 341 # DTB write misses
system.cpu1.dtb.write_acv 29 # DTB write access violations
system.cpu1.dtb.write_accesses 105247 # DTB write accesses
system.cpu1.dtb.data_hits 4158788 # DTB hits
system.cpu1.dtb.data_misses 3333 # DTB misses
system.cpu1.dtb.data_acv 29 # DTB access violations
system.cpu1.dtb.data_accesses 344610 # DTB accesses
system.cpu1.itb.fetch_hits 1960477 # ITB hits
system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
system.cpu1.itb.fetch_accesses 1961693 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.write_acv 0 # DTB write access violations
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.numCycles 3925216965 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 13101094 # Number of instructions committed
system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses
system.cpu1.num_func_calls 409417 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls
system.cpu1.num_int_insts 12083765 # number of integer instructions
system.cpu1.num_fp_insts 172106 # number of float instructions
system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read
system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written
system.cpu1.num_mem_refs 4182249 # number of memory refs
system.cpu1.num_load_insts 2423870 # Number of load instructions
system.cpu1.num_store_insts 1758379 # Number of store instructions
system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles
system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles
system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles
system.cpu1.Branches 1864071 # Number of branches fetched
system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction
system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction
system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction
system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction
system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction
system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction
system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction
system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 13104456 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl
system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed
system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed
system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed
system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed
system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed
system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed
system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed
system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
system.cpu1.kern.callpal::total 71137 # number of callpals executed
system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches
system.cpu1.kern.mode_switch::user 465 # number of protection mode switches
system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches
system.cpu1.kern.mode_good::kernel 889
system.cpu1.kern.mode_good::user 465
system.cpu1.kern.mode_good::idle 424
system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1986 # number of times the context was actually changed
system.cpu1.dcache.tags.replacements 165381 # number of replacements
system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits
system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses
system.cpu1.dcache.overall_misses::total 179876 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks
system.cpu1.dcache.writebacks::total 113645 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 313887 # number of replacements
system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits
system.cpu1.icache.overall_hits::total 12790016 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses
system.cpu1.icache.overall_misses::total 314441 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
system.iobus.trans_dist::WriteReq 55595 # Transaction distribution
system.iobus.trans_dist::WriteResp 55595 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41694 # number of replacements
system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
system.iocache.tags.data_accesses 375534 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
system.iocache.demand_misses::total 174 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
system.iocache.overall_misses::total 174 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles
system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 341250 # number of replacements
system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use
system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 35905885 # Number of tag accesses
system.l2c.tags.data_accesses 35905885 # Number of data accesses
system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits
system.l2c.Writeback_hits::total 793586 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 126818 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 46992 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 173810 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 688011 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 313935 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1001946 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 665063 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 108615 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 773678 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.inst 688011 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 791881 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 313935 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 155607 # number of demand (read+write) hits
system.l2c.demand_hits::total 1949434 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 688011 # number of overall hits
system.l2c.overall_hits::cpu0.data 791881 # number of overall hits
system.l2c.overall_hits::cpu1.inst 313935 # number of overall hits
system.l2c.overall_hits::cpu1.data 155607 # number of overall hits
system.l2c.overall_hits::total 1949434 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 2935 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1733 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 4668 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 882 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 893 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1775 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 115542 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 6588 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 122130 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 12999 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 505 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 271618 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 236 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 271854 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.inst 12999 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 387160 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 6824 # number of demand (read+write) misses
system.l2c.demand_misses::total 407488 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 12999 # number of overall misses
system.l2c.overall_misses::cpu0.data 387160 # number of overall misses
system.l2c.overall_misses::cpu1.inst 505 # number of overall misses
system.l2c.overall_misses::cpu1.data 6824 # number of overall misses
system.l2c.overall_misses::total 407488 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 1432000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 13109500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 14541500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1162500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 214000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 1376500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 8812996500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 538144500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9351141000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1038304000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 40757500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 1079061500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 19659409500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 18967000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 19678376500 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1038304000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 28472406000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 40757500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 557111500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 30108579000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1038304000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 28472406000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 40757500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 557111500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 30108579000 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 793586 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 793586 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 2268 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 5376 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 925 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 1842 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 242360 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 53580 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 295940 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 701010 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 314440 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 1015450 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 936681 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 108851 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 1045532 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 701010 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 1179041 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 314440 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 162431 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2356922 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 701010 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 1179041 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 314440 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 162431 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2356922 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944337 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764109 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.868304 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.953514 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973828 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.963626 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.476737 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.122956 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.412685 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018543 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001606 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.013299 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.289979 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002168 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.260015 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.018543 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.328369 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.001606 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.042012 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.172890 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.018543 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.328369 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.001606 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.042012 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.172890 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 487.904600 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7564.627813 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 3115.145673 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1318.027211 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 239.641657 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 775.492958 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76275.263541 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81685.564663 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 76567.108818 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 79875.682745 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80707.920792 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 79906.805391 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72378.890574 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 80368.644068 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 72385.826583 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 79875.682745 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 73541.703688 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 80707.920792 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 81640.020516 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 73888.259286 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 79875.682745 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 73541.703688 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 80707.920792 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 81640.020516 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 73888.259286 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 78873 # number of writebacks
system.l2c.writebacks::total 78873 # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks 324 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 324 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2935 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1733 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 4668 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 882 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 893 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 1775 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 115542 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 6588 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 122130 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12999 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 494 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 13493 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271618 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 236 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 271854 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 12999 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 387160 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 494 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 6824 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 407477 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 12999 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 387160 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 494 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 6824 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 407477 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 14043 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 21242 # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 60572500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35873500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 96446000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 18219500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18324500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 36544000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7657576500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 472264500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8129841000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 908314000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 35012500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 943326500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 16943229500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 16607000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 16959836500 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 908314000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 24600806000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 35012500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 488871500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 26033004000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 908314000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 24600806000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 35012500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 488871500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 26033004000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1403353000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17974000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 1421327000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2195335000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 686710000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2882045000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3598688000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 704684000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 4303372000 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944337 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764109 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.868304 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.953514 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973828 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.963626 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476737 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122956 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.412685 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013288 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.289979 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002168 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260015 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.172885 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.172885 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 7199 # Transaction distribution
system.membus.trans_dist::ReadResp 292720 # Transaction distribution
system.membus.trans_dist::WriteReq 14043 # Transaction distribution
system.membus.trans_dist::WriteResp 14043 # Transaction distribution
system.membus.trans_dist::Writeback 120393 # Transaction distribution
system.membus.trans_dist::CleanEvict 261901 # Transaction distribution
system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution
system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution
system.membus.trans_dist::ReadExReq 122456 # Transaction distribution
system.membus.trans_dist::ReadExResp 121630 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 21449 # Total snoops (count)
system.membus.snoop_fanout::samples 880387 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 880387 # Request fanout histogram
system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 480853 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
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