sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
Nilay Vaish de489e1997 stats: updates due to recent chagnesets
2015-11-16 05:08:57 -06:00

1881 lines
218 KiB
Text
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 5.140310 # Number of seconds simulated
sim_ticks 5140310077000 # Number of ticks simulated
final_tick 5140310077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 193642 # Simulator instruction rate (inst/s)
host_op_rate 384932 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4095276555 # Simulator tick rate (ticks/s)
host_mem_usage 1038092 # Number of bytes of host memory used
host_seconds 1255.18 # Real time elapsed on the host
sim_insts 243055842 # Number of instructions simulated
sim_ops 483158927 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 444160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5333440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 157504 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1822656 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 355968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 3200064 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
system.physmem.bytes_read::total 11344576 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 444160 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 157504 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 355968 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 957632 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9154432 # Number of bytes written to this memory
system.physmem.bytes_written::total 9154432 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6940 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 83335 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2461 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 28479 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5562 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 50001 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
system.physmem.num_reads::total 177259 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143038 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143038 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 86407 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1037572 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 30641 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 354581 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 411 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 69250 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 622543 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5516 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2206983 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 86407 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 30641 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 69250 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 186298 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1780910 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1780910 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1780910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 86407 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1037572 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 30641 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 354581 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 411 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 69250 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 622543 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5516 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3987893 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 86979 # Number of read requests accepted
system.physmem.writeReqs 83143 # Number of write requests accepted
system.physmem.readBursts 86979 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 83143 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5559296 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
system.physmem.bytesWritten 5321152 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5566656 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 5321152 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 33940 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5203 # Per bank write bursts
system.physmem.perBankRdBursts::1 4657 # Per bank write bursts
system.physmem.perBankRdBursts::2 5413 # Per bank write bursts
system.physmem.perBankRdBursts::3 5303 # Per bank write bursts
system.physmem.perBankRdBursts::4 5134 # Per bank write bursts
system.physmem.perBankRdBursts::5 4786 # Per bank write bursts
system.physmem.perBankRdBursts::6 5593 # Per bank write bursts
system.physmem.perBankRdBursts::7 5448 # Per bank write bursts
system.physmem.perBankRdBursts::8 5260 # Per bank write bursts
system.physmem.perBankRdBursts::9 4897 # Per bank write bursts
system.physmem.perBankRdBursts::10 5208 # Per bank write bursts
system.physmem.perBankRdBursts::11 5207 # Per bank write bursts
system.physmem.perBankRdBursts::12 5484 # Per bank write bursts
system.physmem.perBankRdBursts::13 6574 # Per bank write bursts
system.physmem.perBankRdBursts::14 6603 # Per bank write bursts
system.physmem.perBankRdBursts::15 6094 # Per bank write bursts
system.physmem.perBankWrBursts::0 5594 # Per bank write bursts
system.physmem.perBankWrBursts::1 5124 # Per bank write bursts
system.physmem.perBankWrBursts::2 5270 # Per bank write bursts
system.physmem.perBankWrBursts::3 4838 # Per bank write bursts
system.physmem.perBankWrBursts::4 5433 # Per bank write bursts
system.physmem.perBankWrBursts::5 5211 # Per bank write bursts
system.physmem.perBankWrBursts::6 5102 # Per bank write bursts
system.physmem.perBankWrBursts::7 5101 # Per bank write bursts
system.physmem.perBankWrBursts::8 5096 # Per bank write bursts
system.physmem.perBankWrBursts::9 5186 # Per bank write bursts
system.physmem.perBankWrBursts::10 5320 # Per bank write bursts
system.physmem.perBankWrBursts::11 5088 # Per bank write bursts
system.physmem.perBankWrBursts::12 4612 # Per bank write bursts
system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
system.physmem.perBankWrBursts::14 5353 # Per bank write bursts
system.physmem.perBankWrBursts::15 5452 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
system.physmem.totGap 5136428721000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 86979 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 83143 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 81214 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4352 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 808 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 172 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 122 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1825 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4081 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4013 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4467 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4472 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5576 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5555 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6628 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4990 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4540 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4569 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4085 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 103 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 101 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 86 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 39730 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 273.859753 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 164.661250 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 301.445638 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 16103 40.53% 40.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9824 24.73% 65.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4113 10.35% 75.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2266 5.70% 81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1547 3.89% 85.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1072 2.70% 87.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 721 1.81% 89.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 578 1.45% 91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3506 8.82% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 39730 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 21.613337 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 232.441160 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 4016 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 1 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.687484 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.141176 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 13.818199 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 66 1.64% 1.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 4 0.10% 1.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 1 0.02% 1.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 5 0.12% 1.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 3291 81.89% 83.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 104 2.59% 86.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 32 0.80% 87.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 108 2.69% 89.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 15 0.37% 90.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 105 2.61% 92.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 59 1.47% 94.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 4 0.10% 94.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 14 0.35% 94.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 20 0.50% 95.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 2 0.05% 95.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 4 0.10% 95.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 144 3.58% 98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.10% 99.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 15 0.37% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.02% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 3 0.07% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 10 0.25% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.05% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads
system.physmem.totQLat 1059562475 # Total ticks spent queuing
system.physmem.totMemAccLat 2688262475 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 434320000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12197.95 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30947.95 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.08 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.04 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.08 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.04 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing
system.physmem.readRowHits 68770 # Number of row buffer hits during reads
system.physmem.writeRowHits 61507 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.98 # Row buffer hit rate for writes
system.physmem.avgGap 30192618.95 # Average gap between requests
system.physmem.pageHitRate 76.63 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 145673640 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 79307250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 323988600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 270041040 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 96324881400 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2240107908000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 2587635213210 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.890753 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 3686018034728 # Time in different power states
system.physmem_0.memoryStateTime::REF 128007880000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 19864390272 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 154685160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 84187125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 353550600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 268725600 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 250383413280 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 96580278450 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2233317414750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 2581142254965 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.102097 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 3685663172228 # Time in different power states
system.physmem_1.memoryStateTime::REF 128007880000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 20186348022 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu0.numCycles 1072285093 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu0.committedInsts 71949472 # Number of instructions committed
system.cpu0.committedOps 146629560 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 134558000 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 963710 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14252688 # number of instructions that are conditional controls
system.cpu0.num_int_insts 134558000 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 246915381 # number of times the integer registers were read
system.cpu0.num_int_register_writes 115616486 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 83804950 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 55920138 # number of times the CC registers were written
system.cpu0.num_mem_refs 13826864 # number of memory refs
system.cpu0.num_load_insts 10217566 # Number of load instructions
system.cpu0.num_store_insts 3609298 # Number of store instructions
system.cpu0.num_idle_cycles 1017808343.518800 # Number of idle cycles
system.cpu0.num_busy_cycles 54476749.481200 # Number of busy cycles
system.cpu0.not_idle_fraction 0.050804 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.949196 # Percentage of idle cycles
system.cpu0.Branches 15573120 # Number of branches fetched
system.cpu0.op_class::No_OpClass 93861 0.06% 0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 132602488 90.43% 90.50% # Class of executed instruction
system.cpu0.op_class::IntMult 58992 0.04% 90.54% # Class of executed instruction
system.cpu0.op_class::IntDiv 49734 0.03% 90.57% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction
system.cpu0.op_class::MemRead 10215736 6.97% 97.54% # Class of executed instruction
system.cpu0.op_class::MemWrite 3609298 2.46% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 146630109 # Class of executed instruction
system.cpu0.dcache.tags.replacements 1637608 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999082 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19599059 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1638120 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 11.964361 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.195835 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.604713 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.198534 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.359757 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.413290 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.226950 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999998 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 250 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 88196204 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88196204 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4977443 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2399002 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4079601 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11456046 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3466928 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1632244 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2982379 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8081551 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 21705 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9720 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 28160 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 59585 # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8444371 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4031246 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 7061980 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19537597 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8466076 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4040966 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 7090140 # number of overall hits
system.cpu0.dcache.overall_hits::total 19597182 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 370514 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 153427 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 785283 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1309224 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 138238 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 55177 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 133227 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 326642 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 157440 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58723 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 190307 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 406470 # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data 508752 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 208604 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 918510 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1635866 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 666192 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 267327 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1108817 # number of overall misses
system.cpu0.dcache.overall_misses::total 2042336 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2248261000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12713989500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 14962250500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 3673730495 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6566436401 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 10240166896 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 5921991495 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 19280425901 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 25202417396 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 5921991495 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 19280425901 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 25202417396 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5347957 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2552429 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4864884 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 12765270 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3605166 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1687421 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3115606 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8408193 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 179145 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 68443 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 218467 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 466055 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8953123 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4239850 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7980490 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21173463 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 9132268 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4308293 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 8198957 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21639518 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.069281 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060110 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.161419 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.102561 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038344 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.032699 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042761 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.038848 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.878841 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.857984 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.871102 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.872150 # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.056824 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.049201 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115094 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.077260 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072949 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.062049 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135239 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.094380 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14653.620288 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16190.328200 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11428.335029 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 66580.830690 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 49287.579852 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 31349.816913 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28388.676607 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20990.980938 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 15406.162483 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 22152.612699 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17388.284903 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12339.995670 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 206528 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 21989 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.392333 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1548069 # number of writebacks
system.cpu0.dcache.writebacks::total 1548069 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 363845 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 363915 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1660 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33563 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 35223 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1730 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 397408 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 399138 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1730 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 397408 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 399138 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 153357 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 421438 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 574795 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 53517 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99664 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 153181 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58722 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186898 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 245620 # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 206874 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 521102 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 727976 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 265596 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 708000 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 973596 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 176326 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 193522 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3494 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2876 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 6370 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2091939500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 6052493500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 8144433000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3446784995 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5707366401 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9154151396 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 1012257500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2960769500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3973027000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 5538724495 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11759859901 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 17298584396 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6550981995 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 14720629401 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 21271611396 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30675451000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 32998770000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63674221000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 673827500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 612008500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1285836000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31349278500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33610778500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64960057000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060083 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086629 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045028 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031715 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031989 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018218 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.857969 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855498 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.527019 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.048793 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065297 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.034382 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061648 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086352 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.044992 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13640.978240 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14361.527674 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14169.282962 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 64405.422483 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 57266.078032 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59760.357982 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17238.130513 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15841.632869 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16175.502809 # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26773.420029 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 22567.289899 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23762.575134 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24665.213313 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20791.849436 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21848.499168 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173970.095165 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170516.892136 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172163.215699 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192852.747567 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212798.504868 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201858.084772 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174336.995329 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171136.052811 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172665.999500 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 862096 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.743965 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 129388053 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 862608 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 149.996352 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 149036221500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.474426 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 126.886783 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 237.382757 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286083 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.247826 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.463638 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 277 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 131137351 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 131137351 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 87656735 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38708289 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3023029 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 129388053 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 87656735 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 38708289 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3023029 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 129388053 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 87656735 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 38708289 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3023029 # number of overall hits
system.cpu0.icache.overall_hits::total 129388053 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 322601 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 163645 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 400432 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 886678 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 322601 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 163645 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 400432 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 886678 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 322601 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 163645 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 400432 # number of overall misses
system.cpu0.icache.overall_misses::total 886678 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424283000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5943999964 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 8368282964 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2424283000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 5943999964 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 8368282964 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2424283000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 5943999964 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 8368282964 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 87979336 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 38871934 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3423461 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 130274731 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 87979336 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 38871934 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3423461 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 130274731 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 87979336 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 38871934 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3423461 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 130274731 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003667 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004210 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116967 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.006806 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003667 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004210 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116967 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.006806 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003667 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004210 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116967 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.006806 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14814.280913 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14843.968424 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9437.792484 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14814.280913 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14843.968424 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9437.792484 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14814.280913 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14843.968424 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9437.792484 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 12787 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 569 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.472759 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 862096 # number of writebacks
system.cpu0.icache.writebacks::total 862096 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24058 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 24058 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 24058 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 24058 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 24058 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 24058 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 163645 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376374 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 540019 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 163645 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 376374 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 540019 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 163645 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 376374 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 540019 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2260638000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5253786466 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7514424466 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2260638000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5253786466 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 7514424466 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2260638000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5253786466 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 7514424466 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.109940 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004145 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.109940 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.004145 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004210 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.109940 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.004145 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13814.280913 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13958.951644 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13915.111257 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13814.280913 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13958.951644 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13915.111257 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13814.280913 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13958.951644 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13915.111257 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 2606017773 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.committedInsts 35434857 # Number of instructions committed
system.cpu1.committedOps 68967174 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 63950727 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 471160 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6540311 # number of instructions that are conditional controls
system.cpu1.num_int_insts 63950727 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 118144335 # number of times the integer registers were read
system.cpu1.num_int_register_writes 55187205 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 36132607 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26987111 # number of times the CC registers were written
system.cpu1.num_mem_refs 4484202 # number of memory refs
system.cpu1.num_load_insts 2795233 # Number of load instructions
system.cpu1.num_store_insts 1688969 # Number of store instructions
system.cpu1.num_idle_cycles 2475079638.158952 # Number of idle cycles
system.cpu1.num_busy_cycles 130938134.841048 # Number of busy cycles
system.cpu1.not_idle_fraction 0.050245 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.949755 # Percentage of idle cycles
system.cpu1.Branches 7181922 # Number of branches fetched
system.cpu1.op_class::No_OpClass 31577 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 64399053 93.38% 93.42% # Class of executed instruction
system.cpu1.op_class::IntMult 30119 0.04% 93.47% # Class of executed instruction
system.cpu1.op_class::IntDiv 23752 0.03% 93.50% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.50% # Class of executed instruction
system.cpu1.op_class::MemRead 2793873 4.05% 97.55% # Class of executed instruction
system.cpu1.op_class::MemWrite 1688969 2.45% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 68967343 # Class of executed instruction
system.cpu2.branchPred.lookups 28923833 # Number of BP lookups
system.cpu2.branchPred.condPredicted 28923833 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 299320 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26177104 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 25594852 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 97.775720 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 576883 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 63148 # Number of incorrect RAS predictions.
system.cpu2.numCycles 157005173 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 10541640 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 142873863 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 28923833 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26171735 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 144747848 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 631807 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 102981 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 10810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 7821 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 69710 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 26 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 1766 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3423471 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 155018 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 2920 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 155797854 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.805083 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.007319 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 100986987 64.82% 64.82% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 876917 0.56% 65.38% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23450339 15.05% 80.43% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 581596 0.37% 80.81% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 798015 0.51% 81.32% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 839359 0.54% 81.86% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 536249 0.34% 82.20% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 727748 0.47% 82.67% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27000644 17.33% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 155797854 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.184222 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.909995 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 9166837 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 95859954 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 22256485 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 3994112 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 316555 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 278482972 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 316555 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 10781931 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 77376747 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 5125883 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 24368379 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 13624506 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 277324695 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 194123 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 5339465 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 70652 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 6671965 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 331399724 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 605057293 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 371622887 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 206 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 320041085 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 11358639 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 162877 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 164126 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 19798687 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6564509 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3714734 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 445796 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 396085 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 275510749 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 407738 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 273563069 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 95252 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 8356294 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 12697185 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 62746 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 155797854 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.755885 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.385565 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 93882941 60.26% 60.26% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 5118927 3.29% 63.55% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3721264 2.39% 65.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 3253797 2.09% 68.02% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 23197295 14.89% 82.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 2207034 1.42% 84.33% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 23724652 15.23% 99.56% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 467591 0.30% 99.86% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 224353 0.14% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 155797854 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 1207723 81.78% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 207267 14.03% 95.81% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 61876 4.19% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 77671 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 263072310 96.17% 96.19% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 56421 0.02% 96.21% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 50248 0.02% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 74 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.23% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 6863613 2.51% 98.74% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3442732 1.26% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 273563069 # Type of FU issued
system.cpu2.iq.rate 1.742383 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 1476866 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.005399 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 704495801 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 284279079 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 272064636 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 309 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 294 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 274962115 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 149 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 723478 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 1134849 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 5659 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 5111 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 595348 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 712058 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 23525 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 316555 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 69932049 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 4483827 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 275918487 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 35063 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6564509 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3714734 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 243249 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 162438 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 4010481 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 5111 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 167096 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 181001 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 348097 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 273015158 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 6728091 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 497866 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
system.cpu2.iew.exec_refs 10090158 # number of memory reference insts executed
system.cpu2.iew.exec_branches 27708578 # Number of branches executed
system.cpu2.iew.exec_stores 3362067 # Number of stores executed
system.cpu2.iew.exec_rate 1.738893 # Inst execution rate
system.cpu2.iew.wb_sent 272843265 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 272064754 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 212267822 # num instructions producing a value
system.cpu2.iew.wb_consumers 348193993 # num instructions consuming a value
system.cpu2.iew.wb_rate 1.732839 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.609625 # average fanout of values written-back
system.cpu2.commit.commitSquashedInsts 8353767 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 344992 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 303032 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 154549869 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.731235 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.636337 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 97453895 63.06% 63.06% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4255487 2.75% 65.81% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1275451 0.83% 66.64% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24388605 15.78% 82.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 953115 0.62% 83.03% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 708142 0.46% 83.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 433200 0.28% 83.77% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23018173 14.89% 98.66% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 2063801 1.34% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 154549869 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 135671513 # Number of instructions committed
system.cpu2.commit.committedOps 267562193 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 8549046 # Number of memory references committed
system.cpu2.commit.loads 5429660 # Number of loads committed
system.cpu2.commit.membars 149565 # Number of memory barriers committed
system.cpu2.commit.branches 27339925 # Number of branches committed
system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 244518367 # Number of committed integer instructions.
system.cpu2.commit.function_calls 438140 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 46308 0.02% 0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 258864003 96.75% 96.77% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 54521 0.02% 96.79% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 48349 0.02% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.80% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 5429610 2.03% 98.83% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 3119386 1.17% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 267562193 # Class of committed instruction
system.cpu2.commit.bw_lim_events 2063801 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 428372162 # The number of ROB reads
system.cpu2.rob.rob_writes 553085882 # The number of ROB writes
system.cpu2.timesIdled 112358 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 1207319 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4910585893 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 135671513 # Number of Instructions Simulated
system.cpu2.committedOps 267562193 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.157245 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.157245 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.864121 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.864121 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 363757841 # number of integer regfile reads
system.cpu2.int_regfile_writes 218039219 # number of integer regfile writes
system.cpu2.fp_regfile_reads 73086 # number of floating regfile reads
system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes
system.cpu2.cc_regfile_reads 138801079 # number of cc regfile reads
system.cpu2.cc_regfile_writes 106740366 # number of cc regfile writes
system.cpu2.misc_regfile_reads 88776769 # number of misc regfile reads
system.cpu2.misc_regfile_writes 143860 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 3545348 # Transaction distribution
system.iobus.trans_dist::ReadResp 3545348 # Transaction distribution
system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
system.iobus.trans_dist::WriteResp 57726 # Transaction distribution
system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066648 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 7110880 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 7209436 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533324 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 3561720 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 6596152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2378420 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 5416500 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 921000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 40500 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 21000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 199977500 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 507000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11026500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 144387481 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1052000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 283491000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 31080000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 979000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 47579 # number of replacements
system.iocache.tags.tagsinuse 0.099877 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 5000697713509 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.099877 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006242 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.006242 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 428706 # Number of tag accesses
system.iocache.tags.data_accesses 428706 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses
system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses
system.iocache.demand_misses::total 914 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses
system.iocache.overall_misses::total 914 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126880776 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 126880776 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3631478705 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 3631478705 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 126880776 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 126880776 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 126880776 # number of overall miss cycles
system.iocache.overall_miss_latency::total 126880776 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 138819.229759 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 77728.568172 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 77728.568172 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 138819.229759 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138819.229759 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 138819.229759 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 769 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 71 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.830986 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 756 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 756 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 27936 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 27936 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 756 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 756 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 756 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 756 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 89080776 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 2234678705 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2234678705 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 89080776 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 89080776 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 89080776 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.827133 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.597945 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.597945 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.827133 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.827133 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.827133 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 117831.714286 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79992.794423 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79992.794423 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 117831.714286 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117831.714286 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 117831.714286 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 104623 # number of replacements
system.l2c.tags.tagsinuse 64807.193930 # Cycle average of tags in use
system.l2c.tags.total_refs 4639141 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 168699 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 27.499517 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 51005.580247 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.135096 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1646.367272 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 4933.030076 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 515.170725 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1886.196797 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.248761 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 884.127622 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 3927.337333 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.778283 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.025122 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.075272 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.007861 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.028781 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000141 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.013491 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.059926 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.988879 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 64076 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6926 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54004 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.977722 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 41427151 # Number of tag accesses
system.l2c.tags.data_accesses 41427151 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 20684 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 10937 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 10806 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 5737 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 57444 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 12625 # number of ReadReq hits
system.l2c.ReadReq_hits::total 118233 # number of ReadReq hits
system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits
system.l2c.WriteReq_hits::total 2 # number of WriteReq hits
system.l2c.WritebackDirty_hits::writebacks 1548069 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 1548069 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 861756 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 861756 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 31 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 115 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 276 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 69082 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 29187 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 61537 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 159806 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 315648 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 161184 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 370798 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 847630 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 512537 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 207468 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 595557 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 1315562 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 20684 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 10939 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 315648 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 581619 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 10806 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 5737 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 161184 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 236655 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 57444 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 12625 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 370798 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 657094 # number of demand (read+write) hits
system.l2c.demand_hits::total 2441233 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 20684 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 10939 # number of overall hits
system.l2c.overall_hits::cpu0.inst 315648 # number of overall hits
system.l2c.overall_hits::cpu0.data 581619 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 10806 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 5737 # number of overall hits
system.l2c.overall_hits::cpu1.inst 161184 # number of overall hits
system.l2c.overall_hits::cpu1.data 236655 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 57444 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 12625 # number of overall hits
system.l2c.overall_hits::cpu2.inst 370798 # number of overall hits
system.l2c.overall_hits::cpu2.data 657094 # number of overall hits
system.l2c.overall_hits::total 2441233 # number of overall hits
system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 33 # number of ReadReq misses
system.l2c.ReadReq_misses::total 38 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 707 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 151 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 525 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1383 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 68319 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 24150 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 37538 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 130007 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 6940 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 2461 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 5563 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 14964 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 15417 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 4611 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 12729 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 32757 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 6940 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 83736 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2461 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 28761 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 33 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 5563 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 50267 # number of demand (read+write) misses
system.l2c.demand_misses::total 177766 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu0.inst 6940 # number of overall misses
system.l2c.overall_misses::cpu0.data 83736 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2461 # number of overall misses
system.l2c.overall_misses::cpu1.data 28761 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 33 # number of overall misses
system.l2c.overall_misses::cpu2.inst 5563 # number of overall misses
system.l2c.overall_misses::cpu2.data 50267 # number of overall misses
system.l2c.overall_misses::total 177766 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 4629000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 4629000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 6534500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 20109000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 26643500 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 3047020000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 4863678000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 7910698000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 320798500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 758990000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 1079788500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 606156000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data 1752917000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 2359073000 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 320798500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 3653176000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 4629000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 758990000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 6616595000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 11354188500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 320798500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 3653176000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 4629000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 758990000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 6616595000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 11354188500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 20684 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 10942 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 10806 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 5737 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 57477 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 12625 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 118271 # number of ReadReq accesses(hits+misses)
system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 1548069 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 1548069 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 861756 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 861756 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 837 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 182 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 640 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1659 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 137401 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 53337 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 99075 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 289813 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 322588 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 163645 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu2.inst 376361 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 862594 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 527954 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 212079 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu2.data 608286 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 1348319 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 20684 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 10944 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 322588 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 665355 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 10806 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 5737 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 163645 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 265416 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 57477 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 12625 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 376361 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 707361 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2618999 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 20684 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 10944 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 322588 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 665355 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 10806 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 5737 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 163645 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 265416 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 57477 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 12625 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 376361 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 707361 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2618999 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000457 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000574 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.000321 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844683 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829670 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.820312 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.833635 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.497223 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.452781 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.378885 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.448589 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.021514 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.015039 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.014781 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.017348 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.029201 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021742 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.020926 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.024295 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000457 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.021514 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.125852 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.015039 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.108362 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000574 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.014781 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.071063 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.067876 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000457 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.021514 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.125852 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.015039 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.108362 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000574 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.014781 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.071063 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.067876 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 140272.727273 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 121815.789474 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 43274.834437 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 38302.857143 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 19265.003615 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126170.600414 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 129566.785657 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 60848.246633 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130352.905323 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 136435.376595 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 72159.081796 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131458.685751 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 137710.503575 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 72017.370333 # average ReadSharedReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 130352.905323 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 127018.392963 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 140272.727273 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 136435.376595 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 131629.001134 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 63871.541802 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 130352.905323 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 127018.392963 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 140272.727273 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 136435.376595 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 131629.001134 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 63871.541802 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 96371 # number of writebacks
system.l2c.writebacks::total 96371 # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 33 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 33 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 151 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 525 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 676 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 24150 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 37538 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 61688 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2461 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5562 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 8023 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 4611 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu2.data 12729 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 17340 # number of ReadSharedReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 2461 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 28761 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 33 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 5562 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 50267 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 87084 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 2461 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 28761 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 33 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 5562 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 50267 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 87084 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 176326 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu2.data 193522 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 369848 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3494 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2876 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 6370 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 179820 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu2.data 196398 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 376218 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 4299000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 4299000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10668000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 37173000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 47841000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2805520000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4488298000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7293818000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 296188500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 703281000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 999469500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 560046000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1625627000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 2185673000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 296188500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 3365566000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4299000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 703281000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 6113925000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 10483259500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 296188500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 3365566000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4299000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 703281000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 6113925000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 10483259500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28471375500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30579727000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 59051102500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 633646000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 578915000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1212561000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29105021500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31158642000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 60263663500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.000279 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829670 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.820312 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.407474 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452781 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.378885 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.212854 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014778 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.009301 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021742 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.020926 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.012860 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000574 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014778 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.071063 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.033251 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015039 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.108362 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000574 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014778 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.071063 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.033251 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 130272.727273 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70649.006623 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70805.714286 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70770.710059 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116170.600414 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119566.785657 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 118237.226041 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 126443.905070 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124575.532843 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121458.685751 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 127710.503575 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126048.039216 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117018.392963 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 126443.905070 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 121629.001134 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 120381.005696 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120352.905323 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117018.392963 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 130272.727273 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 126443.905070 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 121629.001134 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 120381.005696 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161470.092329 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 158016.799124 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159663.165679 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181352.604465 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 201291.724618 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 190354.945055 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161856.420309 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158650.505606 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 160182.828839 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 5063565 # Transaction distribution
system.membus.trans_dist::ReadResp 5112237 # Transaction distribution
system.membus.trans_dist::WriteReq 13898 # Transaction distribution
system.membus.trans_dist::WriteResp 13898 # Transaction distribution
system.membus.trans_dist::WritebackDirty 143038 # Transaction distribution
system.membus.trans_dist::CleanEvict 8555 # Transaction distribution
system.membus.trans_dist::UpgradeReq 1675 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1675 # Transaction distribution
system.membus.trans_dist::ReadExReq 129715 # Transaction distribution
system.membus.trans_dist::ReadExResp 129715 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 48672 # Transaction distribution
system.membus.trans_dist::MessageReq 1644 # Transaction distribution
system.membus.trans_dist::MessageResp 1644 # Transaction distribution
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110880 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044046 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 462505 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 10617431 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141987 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141987 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10762706 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561720 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6088089 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17503808 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 27153617 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 30185345 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 665 # Total snoops (count)
system.membus.snoop_fanout::samples 5458032 # Request fanout histogram
system.membus.snoop_fanout::mean 1.000301 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.017353 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 5456388 99.97% 99.97% # Request fanout histogram
system.membus.snoop_fanout::2 1644 0.03% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
system.membus.snoop_fanout::total 5458032 # Request fanout histogram
system.membus.reqLayer0.occupancy 219245500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 286800000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 2376580 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 547442853 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1397580 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1208317879 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer4.occupancy 52360943 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.toL2Bus.snoop_filter.tot_requests 5045447 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2544703 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1173 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1173 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 5213999 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 7425168 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13900 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13900 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1631215 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 861756 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 94957 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 289813 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 289813 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 862620 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 1349075 # Transaction distribution
system.toL2Bus.trans_dist::MessageReq 979 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 27936 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586983 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15072215 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 70159 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 206201 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17935558 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110359232 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213581393 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 258600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 748792 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 324948017 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 226396 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 8918852 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.005051 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.070893 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 8873800 99.49% 99.49% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 45052 0.51% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 8918852 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 3217820998 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 406876 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 810576399 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1832733252 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 23881478 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 87500568 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink