78275c9d2f
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).
This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.
PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.
The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.
Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:
* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.
* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.
* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.
331 lines
11 KiB
C++
331 lines
11 KiB
C++
/*
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* Copyright (c) 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Sandberg
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*/
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#ifndef __DEV_PCI_HOST_HH__
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#define __DEV_PCI_HOST_HH__
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#include "dev/io_device.hh"
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#include "dev/pci/types.hh"
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struct PciHostParams;
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struct GenericPciHostParams;
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class PciDevice;
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class Platform;
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/**
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* The PCI host describes the interface between PCI devices and a
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* simulated system.
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*
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* The PCI host controller has three main responsibilities:
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* <ol>
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* <li>Expose a configuration memory space that allows devices to
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* be discovered and configured.
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* <li>Map and deliver interrupts to the CPU.
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* <li>Map memory addresses from the PCI bus's various memory
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* spaces (Legacy IO, non-prefetchable memory, and
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* prefetchable memory) to physical memory.
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* </ol>
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*
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* PCI devices need to register themselves with a PCI host using the
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* PciHost::registerDevice() call. This call returns a
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* PciHost::DeviceInterface that provides for common functionality
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* such as interrupt delivery and memory mapping.
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*
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* The PciHost class itself provides very little functionality. Simple
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* PciHost functionality is implemented by the GenericPciHost class.
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*/
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class PciHost : public PioDevice
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{
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public:
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PciHost(const PciHostParams *p);
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virtual ~PciHost();
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public:
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/**
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* @{
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* @name Device interface
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*/
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/**
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* Callback interface from PCI devices to the host.
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*
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* Devices get an instance of this object when they register
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* themselves with the host using the PciHost::registerDevice()
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* call.
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*/
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class DeviceInterface
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{
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friend class ::PciHost;
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protected:
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/**
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* Instantiate a device interface
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*
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* @param host PCI host that this device belongs to.
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* @param bus_addr The device's position on the PCI bus
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* @param pin Interrupt pin
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*/
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DeviceInterface(PciHost &host, PciBusAddr &bus_addr, PciIntPin pin);
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public:
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DeviceInterface() = delete;
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void operator=(const DeviceInterface &) = delete;
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const std::string name() const;
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/**
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* Post a PCI interrupt to the CPU.
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*/
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void postInt();
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/**
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* Clear a posted PCI interrupt
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*/
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void clearInt();
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/**
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* Calculate the physical address of an IO location on the PCI
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* bus.
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*
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* @param addr Address in the PCI IO address space
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* @return Address in the system's physical address space.
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*/
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Addr pioAddr(Addr addr) const { return host.pioAddr(busAddr, addr); }
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/**
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* Calculate the physical address of a non-prefetchable memory
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* location in the PCI address space.
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*
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* @param addr Address in the PCI memory address space
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* @return Address in the system's physical address space.
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*/
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Addr memAddr(Addr addr) const { return host.memAddr(busAddr, addr); }
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/**
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* Calculate the physical address of a prefetchable memory
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* location in the PCI address space.
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*
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* @param addr Address in the PCI DMA memory address space
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* @return Address in the system's physical address space.
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*/
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Addr dmaAddr(Addr addr) const { return host.dmaAddr(busAddr, addr); }
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protected:
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PciHost &host;
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const PciBusAddr busAddr;
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const PciIntPin interruptPin;
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};
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/**
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* Register a PCI device with the host.
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*
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* @param device Device to register
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* @param bus_addr The device's position on the PCI bus
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* @param pin Interrupt pin
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* @return A device-specific DeviceInterface instance.
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*/
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virtual DeviceInterface registerDevice(PciDevice *device,
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PciBusAddr bus_addr, PciIntPin pin);
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/** @} */
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protected:
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/**
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* @{
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* @name PciHost controller interface
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*/
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/**
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* Post an interrupt to the CPU.
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*
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* @param bus_addr The device's position on the PCI bus
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* @param pin PCI interrupt pin
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*/
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virtual void postInt(const PciBusAddr &bus_addr, PciIntPin pin) = 0;
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/**
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* Post an interrupt to the CPU.
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*
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* @param bus_addr The device's position on the PCI bus
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* @param pin PCI interrupt pin
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*/
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virtual void clearInt(const PciBusAddr &bus_addr, PciIntPin pin) = 0;
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/**
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* Calculate the physical address of an IO location on the PCI
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* bus.
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*
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* @param bus_addr The device's position on the PCI bus
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* @param pci_addr Address in the PCI IO address space
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* @return Address in the system's physical address space.
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*/
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virtual Addr pioAddr(const PciBusAddr &bus_addr, Addr pci_addr) const = 0;
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/**
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* Calculate the physical address of a non-prefetchable memory
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* location in the PCI address space.
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*
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* @param bus_addr The device's position on the PCI bus
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* @param pci_addr Address in the PCI memory address space
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* @return Address in the system's physical address space.
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*/
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virtual Addr memAddr(const PciBusAddr &bus_addr, Addr pci_addr) const = 0;
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/**
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* Calculate the physical address of a prefetchable memory
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* location in the PCI address space.
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*
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* @param bus_addr The device's position on the PCI bus
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* @param pci_addr Address in the PCI DMA memory address space
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* @return Address in the system's physical address space.
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*/
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virtual Addr dmaAddr(const PciBusAddr &bus_addr, Addr pci_addr) const = 0;
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/** @} */
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protected:
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/**
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* Retrieve a PCI device from its bus address.
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*
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* @return Pointer to a PciDevice instance or nullptr if the
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* device doesn't exist.
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*/
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PciDevice *getDevice(const PciBusAddr &addr);
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/**
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* Retrieve a PCI device from its bus address.
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*
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* @return Pointer to a constant PciDevice instance or nullptr if
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* the device doesn't exist.
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*/
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const PciDevice *getDevice(const PciBusAddr &addr) const;
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private:
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/** Currently registered PCI devices */
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std::map<PciBusAddr, PciDevice *> devices;
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};
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/**
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* Configurable generic PCI host interface
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*
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* The GenericPciHost provides a configurable generic PCI host
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* implementation.
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*
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* The generic controller binds to one range of physical addresses to
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* implement the PCI subsystem's configuraiton space. The base
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* address, size and mapping between memory addresses and PCI devices
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* are all configurable as simulation parameters. The basic
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* implementation supports both the Configuration Access Mechanism
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* (CAM) and Enhanced Configuration Access Mechanism (ECAM)
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* configuration space layout. The layouts can be configured by
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* changing the number of bits allocated to each device in the
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* configuration space. ECAM uses 12 bits per device, while CAM uses 8
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* bits per device.
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*
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* Interrupts are delivered via the Platform::postInt() and
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* Platform::clearInt() calls. Interrupt numbers are mapped statically
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* using the interrupt line (PciDevice::interruptLine()) returned from
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* the device. Implementations may override mapPciInterrupt() to
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* dynamically map a PciBusAddr and PciIntPin to a platform-specific
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* interrupt.
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*
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* All PCI memory spaces (IO, prefetchable, and non-prefetchable)
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* support a simple base+offset mapping that can be configured using
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* simulation parameters. The base defaults to 0 for all of them.
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*/
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class GenericPciHost : public PciHost
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{
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public:
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GenericPciHost(const GenericPciHostParams *p);
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virtual ~GenericPciHost();
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public: // PioDevice
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Tick read(PacketPtr pkt) override;
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Tick write(PacketPtr pkt) override;
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AddrRangeList getAddrRanges() const override;
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protected: // PciHost
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Addr pioAddr(const PciBusAddr &bus_addr, Addr pci_addr) const override {
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return pciPioBase + pci_addr;
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}
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Addr memAddr(const PciBusAddr &bus_addr, Addr pci_addr) const override {
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return pciMemBase + pci_addr;
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}
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Addr dmaAddr(const PciBusAddr &bus_addr, Addr pci_addr) const override {
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return pciDmaBase + pci_addr;
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}
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protected: // Configuration address space handling
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/**
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* Decode a configuration space address.
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*
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*
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* @param addr Offset into the configuration space
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* @return Tuple containing the PCI bus address and an offset into
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* the device's configuration space.
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*/
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virtual std::pair<PciBusAddr, Addr> decodeAddress(Addr address);
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protected: // Interrupt handling
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void postInt(const PciBusAddr &addr, PciIntPin pin) override;
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void clearInt(const PciBusAddr &addr, PciIntPin pin) override;
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virtual uint32_t mapPciInterrupt(const PciBusAddr &bus_addr,
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PciIntPin pin) const;
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protected:
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Platform &platform;
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const Addr confBase;
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const Addr confSize;
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const uint8_t confDeviceBits;
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const Addr pciPioBase;
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const Addr pciMemBase;
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const Addr pciDmaBase;
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};
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#endif // __DEV_PCI_HOST_HH__
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