78275c9d2f
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).
This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.
PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.
The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.
Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:
* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.
* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.
* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.
351 lines
10 KiB
C++
351 lines
10 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Andrew Schultz
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*/
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/** @file
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* Tsunami PChip (pci)
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*/
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#include "dev/alpha/tsunami_pchip.hh"
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "debug/Tsunami.hh"
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#include "dev/alpha/tsunami.hh"
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#include "dev/alpha/tsunami_cchip.hh"
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#include "dev/alpha/tsunamireg.h"
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#include "dev/pcidev.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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using namespace std;
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//Should this be AlphaISA?
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using namespace TheISA;
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TsunamiPChip::TsunamiPChip(const Params *p)
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: GenericPciHost(p),
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pioRange(RangeSize(p->pio_addr, 0x1000)),
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pioDelay(p->pio_latency)
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{
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for (int i = 0; i < 4; i++) {
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wsba[i] = 0;
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wsm[i] = 0;
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tba[i] = 0;
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}
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// initialize pchip control register
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pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
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//Set back pointer in tsunami
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p->tsunami->pchip = this;
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}
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Tick
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TsunamiPChip::read(PacketPtr pkt)
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{
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// We only need to handle our own configuration registers, pass
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// unknown addresses to the generic code.
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if (!pioRange.contains(pkt->getAddr()))
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return GenericPciHost::read(pkt);
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Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;;
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assert(pkt->getSize() == sizeof(uint64_t));
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DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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pkt->set(wsba[0]);
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break;
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case TSDEV_PC_WSBA1:
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pkt->set(wsba[1]);
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break;
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case TSDEV_PC_WSBA2:
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pkt->set(wsba[2]);
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break;
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case TSDEV_PC_WSBA3:
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pkt->set(wsba[3]);
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break;
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case TSDEV_PC_WSM0:
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pkt->set(wsm[0]);
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break;
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case TSDEV_PC_WSM1:
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pkt->set(wsm[1]);
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break;
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case TSDEV_PC_WSM2:
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pkt->set(wsm[2]);
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break;
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case TSDEV_PC_WSM3:
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pkt->set(wsm[3]);
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break;
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case TSDEV_PC_TBA0:
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pkt->set(tba[0]);
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break;
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case TSDEV_PC_TBA1:
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pkt->set(tba[1]);
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break;
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case TSDEV_PC_TBA2:
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pkt->set(tba[2]);
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break;
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case TSDEV_PC_TBA3:
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pkt->set(tba[3]);
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break;
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case TSDEV_PC_PCTL:
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pkt->set(pctl);
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break;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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pkt->set((uint64_t)0x00);
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break;
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case TSDEV_PC_PERRMASK:
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pkt->set((uint64_t)0x00);
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break;
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
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break;
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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TsunamiPChip::write(PacketPtr pkt)
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{
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// We only need to handle our own configuration registers, pass
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// unknown addresses to the generic code.
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if (!pioRange.contains(pkt->getAddr()))
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return GenericPciHost::write(pkt);
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Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;
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assert(pkt->getSize() == sizeof(uint64_t));
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DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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wsba[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA1:
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wsba[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA2:
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wsba[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSBA3:
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wsba[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM0:
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wsm[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM1:
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wsm[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM2:
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wsm[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_WSM3:
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wsm[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA0:
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tba[0] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA1:
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tba[1] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA2:
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tba[2] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_TBA3:
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tba[3] = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_PCTL:
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pctl = pkt->get<uint64_t>();
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break;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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break;
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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break; // value ignored, supposted to invalidate SG TLB
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip write reached reading 0x%x\n", daddr);
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} // uint64_t
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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AddrRangeList
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TsunamiPChip::getAddrRanges() const
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{
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return AddrRangeList({
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RangeSize(confBase, confSize),
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pioRange
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});
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}
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#define DMA_ADDR_MASK ULL(0x3ffffffff)
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Addr
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TsunamiPChip::dmaAddr(const PciBusAddr &dev, Addr busAddr) const
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{
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// compare the address to the window base registers
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uint64_t tbaMask = 0;
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uint64_t baMask = 0;
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uint64_t windowMask = 0;
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uint64_t windowBase = 0;
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uint64_t pteEntry = 0;
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Addr pteAddr;
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Addr dmaAddr;
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#if 0
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DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
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for (int i = 0; i < 4; i++) {
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DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
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i, wsba[i], wsm[i]);
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
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i, windowBase, windowMask, (busAddr & windowMask),
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(windowBase & windowMask));
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}
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}
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#endif
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for (int i = 0; i < 4; i++) {
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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if (wsba[i] & 0x1) { // see if enabled
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if (wsba[i] & 0x2) { // see if SG bit is set
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/** @todo
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This currently is faked by just doing a direct
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read from memory, however, to be realistic, this
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needs to actually do a bus transaction. The process
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is explained in the tsunami documentation on page
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10-12 and basically munges the address to look up a
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PTE from a table in memory and then uses that mapping
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to create an address for the SG page
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*/
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tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
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pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
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sys->physProxy.readBlob(pteAddr, (uint8_t*)&pteEntry,
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sizeof(uint64_t));
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dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
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} else {
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
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tbaMask = ~baMask;
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dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
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}
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return (dmaAddr & DMA_ADDR_MASK);
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}
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}
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}
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// if no match was found, then return the original address
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return busAddr;
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}
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void
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TsunamiPChip::serialize(CheckpointOut &cp) const
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{
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SERIALIZE_SCALAR(pctl);
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SERIALIZE_ARRAY(wsba, 4);
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SERIALIZE_ARRAY(wsm, 4);
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SERIALIZE_ARRAY(tba, 4);
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}
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void
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TsunamiPChip::unserialize(CheckpointIn &cp)
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{
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UNSERIALIZE_SCALAR(pctl);
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UNSERIALIZE_ARRAY(wsba, 4);
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UNSERIALIZE_ARRAY(wsm, 4);
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UNSERIALIZE_ARRAY(tba, 4);
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}
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TsunamiPChip *
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TsunamiPChipParams::create()
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{
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return new TsunamiPChip(this);
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}
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