gem5/configs/common
Andreas Sandberg 78275c9d2f dev: Rewrite PCI host functionality
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

  * Configurable configuration space decoding. The number of bits
    dedicated to a device is a prameter, making it possible to support
    both CAM, ECAM, and legacy mappings.

  * Basic interrupt mapping using the interruptLine value from a
    device's configuration space. This behavior is the same as in the
    old implementation. More advanced controllers can override the
    interrupt mapping method to dynamically assign host interrupts to
    PCI devices.

  * Simple (base + addr) remapping from the PCI bus's address space to
    physical addresses for PIO, memory, and DMA.
2015-12-05 00:11:24 +00:00
..
Benchmarks.py config: Specify OS type and release on command line 2015-03-19 04:06:14 -04:00
CacheConfig.py mem: Allow read-only caches and check compliance 2015-07-03 10:14:39 -04:00
Caches.py mem: Add an option to perform clean writebacks from caches 2015-11-06 03:26:43 -05:00
cpu2000.py arm: Add support for ARMv8 (AArch64 & AArch32) 2014-01-24 15:29:34 -06:00
CpuConfig.py kvm, arm: Add support for aarch64 2015-06-01 19:44:19 +01:00
FSConfig.py dev: Rewrite PCI host functionality 2015-12-05 00:11:24 +00:00
HMC.py configs: fix bug introduced due to 276ad9121192 2015-11-04 12:36:28 -06:00
MemConfig.py mem: hmc: top level design 2015-11-03 12:17:56 -06:00
O3_ARM_v7a.py mem: Add an option to perform clean writebacks from caches 2015-11-06 03:26:43 -05:00
Options.py arm, config: Automatically discover available platforms 2015-12-04 00:19:05 +00:00
PlatformConfig.py arm, config: Automatically discover available platforms 2015-12-04 00:19:05 +00:00
SimpleOpts.py config: Add configs scripts used in Learning gem5 2015-09-16 09:35:36 -05:00
Simulation.py config, cpu: fix progress interval for switched CPUs 2015-04-14 11:01:10 -05:00
SysPaths.py config: expand '~' and '~user' in paths 2015-03-23 16:14:19 -07:00