20e9a90edc
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
469 lines
12 KiB
C++
469 lines
12 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output header {{
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/**
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* Base class for general Mips memory-format instructions.
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*/
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class Memory : public MipsStaticInst
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{
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protected:
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/// Memory request flags. See mem_req_base.hh.
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unsigned memAccessFlags;
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/// Pointer to EAComp object.
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const StaticInstPtr eaCompPtr;
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/// Pointer to MemAcc object.
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const StaticInstPtr memAccPtr;
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/// Displacement for EA calculation (signed).
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int32_t disp;
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/// Constructor
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Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr _memAccPtr = nullStaticInstPtr)
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: MipsStaticInst(mnem, _machInst, __opClass),
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memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
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disp(OFFSET)
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{
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//If Bit 15 is 1 then Sign Extend
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int32_t temp = disp & 0x00008000;
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if (temp > 0) {
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disp |= 0xFFFF0000;
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}
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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public:
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const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
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const StaticInstPtr &memAccInst() const { return memAccPtr; }
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};
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}};
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output decoder {{
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std::string
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Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
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flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
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}
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}};
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def format LoadAddress(code) {{
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iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def template LoadStoreDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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protected:
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/**
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* "Fake" effective address computation class for "%(mnemonic)s".
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*/
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class EAComp : public %(base_class)s
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{
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public:
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/// Constructor
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EAComp(MachInst machInst);
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%(BasicExecDeclare)s
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};
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/**
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* "Fake" memory access instruction class for "%(mnemonic)s".
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*/
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class MemAcc : public %(base_class)s
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{
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public:
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/// Constructor
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MemAcc(MachInst machInst);
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%(BasicExecDeclare)s
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};
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public:
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/// Constructor.
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%(class_name)s(MachInst machInst);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template CompleteAccDeclare {{
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Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template LoadStoreConstructor {{
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/** TODO: change op_class to AddrGenOp or something (requires
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* creating new member of OpClass enum in op_class.hh, updating
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* config files, etc.). */
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inline %(class_name)s::EAComp::EAComp(MachInst machInst)
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: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
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{
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%(ea_constructor)s;
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}
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inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
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: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
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{
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%(memacc_constructor)s;
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}
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inline %(class_name)s::%(class_name)s(MachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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new EAComp(machInst), new MemAcc(machInst))
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{
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%(constructor)s;
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}
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}};
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def template EACompExecute {{
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Fault
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%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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xc->setEA(EA);
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}
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return fault;
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}
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}};
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def template LoadMemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template LoadExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template LoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_src_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
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}
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return fault;
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}
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}};
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def template LoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(uint8_t *data,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_src_decl)s;
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%(op_dest_decl)s;
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memcpy(&Mem, data, sizeof(Mem));
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreMemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == NoFault) {
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%(code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_src_decl)s;
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%(op_dest_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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return fault;
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}
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}};
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def template StoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(uint8_t *data,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_dest_decl)s;
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memcpy(&write_result, data, sizeof(write_result));
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// load instructions use Rt as dest, so check for
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// Rt == 31 to detect nops
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def template LoadNopCheckDecode {{
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{
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MipsStaticInst *i = new %(class_name)s(machInst);
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if (RT == 0) {
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i = makeNop(i);
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}
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return i;
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}
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}};
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def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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decode_template = LoadNopCheckDecode,
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exec_template_base = 'Load')
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}};
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def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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exec_template_base = 'Store')
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}};
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//FP loads are offloaded to these formats for now ...
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def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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decode_template = LoadNopCheckDecode,
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exec_template_base = 'Load')
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}};
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//FP stores are offloaded to these formats for now ...
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def format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }},
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mem_flags = [], inst_flags = []) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
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decode_template = LoadNopCheckDecode,
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exec_template_base = 'Store')
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}};
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